<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>PMDEVAFF0</reg_short_name>
        
        <reg_long_name>Performance Monitors Device Affinity register 0</reg_long_name>


        <reg_parent_link id="pmu.xml">PMU</reg_parent_link>

      
            <reg_condition>when FEAT_PMUv3_EXT32 is implemented</reg_condition>
      



    
    <reg_address
        external_access="False"
        mem_map_access="False"
        block_access="True"
        memory_access="True"
        table_id="PMUacccessor0"
    >
  
  <reg_frame>PMU</reg_frame>
  
    
    <reg_offset><hexnumber>0xFA8</hexnumber></reg_offset>
    <reg_access>
    
        
      <reg_access_state>
          <reg_access_level>When FEAT_DoPD is implemented and !IsCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>


          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Copy of the low half of the PE <register_link state="AArch64" id="AArch64-mpidr_el1.xml">MPIDR_EL1</register_link> register that allows a debugger to determine which PE in a multiprocessor system the Performance Monitor component relates to.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>PMU</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>If <xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> is implemented, this register is in the Core power domain. If <xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> is not implemented, this register is in the Debug power domain.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>PMDEVAFF0 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_31" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RAO/WI">
    <field_msb>31</field_msb>
    <field_lsb>31</field_lsb>
    <rel_range>31</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, RAO/WI.</para>
    </field_description>
  </field>
  <field id="fieldset_0-30_30" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>U</field_name>
    <field_msb>30</field_msb>
    <field_lsb>30</field_lsb>
    <rel_range>30</rel_range>
    <field_description order="before">
      <para>Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.</para>
    </field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Processor is part of a multiprocessor system.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Processor is part of a uniprocessor system.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-29_25" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>29</field_msb>
    <field_lsb>25</field_lsb>
    <rel_range>29:25</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-24_24" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>MT</field_name>
    <field_msb>24</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>24</rel_range>
    <field_description order="before">
      <para>Indicates whether the lowest level of affinity consists of logical PEs that are implemented using an interdependent approach, such as multithreading. See the description of Aff0 for more information about affinity levels.</para>
    </field_description>
    <field_description order="after">
      <note>
        <para>This field does not indicate that multithreading is implemented and does not indicate that PEs with different affinity level 0 values, and the same values for affinity level 1 and higher are implemented.</para>
      </note>
    </field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is largely independent.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is very interdependent.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-23_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>Aff2</field_name>
    <field_msb>23</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>23:16</rel_range>
    <field_description order="before">
      <para>Affinity level 2. See the description of Aff0 for more information.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-15_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>Aff1</field_name>
    <field_msb>15</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>15:8</rel_range>
    <field_description order="before">
      <para>Affinity level 1. See the description of Aff0 for more information.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-7_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>Aff0</field_name>
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>Affinity level 0. The value of the <register_link state="AArch32" id="AArch32-mpidr.xml">MPIDR</register_link>.{Aff2, Aff1, Aff0} or <register_link state="AArch64" id="AArch64-mpidr_el1.xml">MPIDR_EL1</register_link>.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_31" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-30_30" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-29_25" msb="29" lsb="25"/>
  <fieldat id="fieldset_0-24_24" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-23_16" msb="23" lsb="16"/>
  <fieldat id="fieldset_0-15_8" msb="15" lsb="8"/>
  <fieldat id="fieldset_0-7_0" msb="7" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>If <xref linkend="#FEAT_PMUv3_EXT64">FEAT_PMUv3_EXT64</xref> is implemented, then the same content is present in the same location, and can be accessed using PMDEVAFF[31:0].</para>
      </access_permission_text>





    
        
        <access_mechanism type="BlockAccessAbstract" table_id="PMUacccessor0">
        
        
        
        
        <access_header>Accessible at offset <hexnumber>0xFA8</hexnumber> from PMU</access_header>
    </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>