PMEVCNTR<n>_EL0 Performance Monitors Event Count Registers PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented 0 30 PMU 0x000 + (8 * n) When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(addrdesc) RAZ/WI RW PMU 0x000 + (8 * n) When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(addrdesc) RAZ/WI When SoftwareLockStatus(addrdesc) RO RW PMU 0x000 + (8 * n) When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW PMEVCNTR<n>_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p5 is implemented PMEVCNTR<n>_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p5 is not implemented PMEVCNTR<n> Architectural AArch32 31 0 31 0 31 0 31 0 Holds event counter <n>, which counts events, where <n> is 0 to 30. PMU PMEVCNTR<n>_EL0 is in the Core power domain. PMEVCNTR<n>_EL0 is a: 64-bit register when FEAT_PMUv3p5 is implemented 32-bit register otherwise When FEAT_PMUv3p5 is implemented EVCNT Event counter n 63 0 63:0 Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30. If the highest implemented Exception level is using AArch32, the optional external interface to the performance monitors is implemented, and the PMCR.LP and HDCR.HLP bits are RAZ/WI, then locations in the external interface to the performance monitors that map to PMEVCNTR<n>_EL0[63:32] return UNKNOWN values on reads. If the implementation does not support AArch64, bits [63:32] of the event counters are not required to be implemented. AU AU EVCNT Event counter n 31 0 31:0 Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30. AU When FEAT_PMUv3p5 is implemented If FEAT_PMUv3p5 is not implemented, when IsCorePowered(), DoubleLockStatus(), OSLockStatus() or !AllowExternalPMUAccess(), 32-bit accesses to 0x004+8×n have a CONSTRAINED UNPREDICTABLE behavior. [63:0] Accessible at offset 0x000 + (8 * n) from PMU When FEAT_PMUv3_EXT64 is implemented [63:0] Accessible at offset 0x000 + (8 * n) from PMU When FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p5 is implemented [31:0] Accessible at offset 0x000 + (8 * n) from PMU When FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p5 is not implemented 2026-03-26 20:27:25 2026-03_rel