PMEVCNTSVR<n>_EL1 Performance Monitors Event Count Saved Value Registers PMU when FEAT_PMUv3_SS is implemented and FEAT_PMUv3_EXT is implemented 0 30 PMU 0x600 + (8 * n) When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMSSAccess(addrdesc) ERROR When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(addrdesc) RAZ/WI RO PMEVCNTSVR<n>_EL1 Architectural AArch64 63 0 63 0 63 0 63 0 Captures the PMU Event counter <n>, PMEVCNTR<n>_EL0. PMU PMEVCNTSVR<n>_EL1 is in the Core power domain. If event counter n is not implemented: When IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalPMUAccess(addrdesc), accesses are RES0. Otherwise, it is CONSTRAINED UNPREDICTABLE whether accesses to this register are RES0 or generate an error response. PMEVCNTSVR<n>_EL1 is a 64-bit register. EVCNT 63 0 63:0 Sampled Event Count. The value of PMEVCNTR<n>_EL0 at the last successful Capture event. AU AU Accessible at offset 0x600 + (8 * n) from PMU 2026-03-26 20:27:25 2026-03_rel