PMIIDR Performance Monitors Implementation Identification Register PMU when (FEAT_PMUv3_EXT32 is implemented and an implementation implements PMIIDR) or FEAT_PMUv3_EXT64 is implemented PMU 0xE08 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO Provides discovery information about the Performance Monitor component. PMU PMIIDR is a: 64-bit register when FEAT_PMUv3_EXT64 is implemented 32-bit register otherwise When FEAT_PMUv3_EXT64 is implemented 63 32 63:32 Reserved, RES0. ProductID 31 20 31:20 Part number, bits [11:0]. The part number is selected by the designer of the component. Matches the part number represented in the Peripheral ID registers PMPIDRn, if those registers are present. This field has an IMPLEMENTATION DEFINED value. RO Variant 19 16 19:16 Component major revision. Defines either a variant of the component defined by PMIIDR.ProductID, or the major revision of the component. When defining a major revision, PMIIDR.Variant and PMIIDR.Revision together form the revision number of the component, with this field being the most significant part. When a component is changed, PMIIDR.Variant or PMIIDR.Revision is increased to ensure that software can differentiate between different revisions of the component. If this field is increased, PMIIDR.Revision should be set to 0b0000. Arm recommends this field matches the PMPIDR2.REVISION field, if present. This field has an IMPLEMENTATION DEFINED value. RO Revision 15 12 15:12 Component minor revision. PMIIDR.Variant and PMIIDR.Revision together form the revision number of the component, with this field being the least significant part. When a component is changed, PMIIDR.Variant or PMIIDR.Revision is increased to ensure that software can differentiate between different revisions of the component. If PMIIDR.Variant field is increased, this field should be set to 0b0000, otherwise the value in this field should be increased. Arm recommends this field matches the PMPIDR3.REVAND field, if present. This field has an IMPLEMENTATION DEFINED value. RO Implementer 11 0 11:0 Contains the JEP106 manufacturer's identification code of the designer of the PMU. The code identifies the designer of the component, which might not be the same as the implementer of the device containing the component. Zero is not a valid JEP106 identification code, meaning a value of zero for PMIIDR indicates this register is not implemented. For an implementation designed by Arm, this field reads as 0x43B. Bits [11:8] contain the JEP106 bank identifier of the designer minus 1. Bit 7 is RES0. Bits [6:0] contain bits [6:0] of the JEP106 manufacturer's identification code of the designer. If PMPIDR4 is implemented, PMPIDR4.DES_2 matches bits [11:8] of this field. If PMPIDR2 is implemented, PMPIDR2.DES_1 matches bits [6:4] of this field. If PMPIDR1 is implemented, PMPIDR1.DES_0 matches bits [3:0] of this field. This field has an IMPLEMENTATION DEFINED value. RO ProductID 31 20 31:20 Part number, bits [11:0]. The part number is selected by the designer of the component. Matches the part number represented in the Peripheral ID registers PMPIDRn, if those registers are present. This field has an IMPLEMENTATION DEFINED value. RO Variant 19 16 19:16 Component major revision. Defines either a variant of the component defined by PMIIDR.ProductID, or the major revision of the component. When defining a major revision, PMIIDR.Variant and PMIIDR.Revision together form the revision number of the component, with this field being the most significant part. When a component is changed, PMIIDR.Variant or PMIIDR.Revision is increased to ensure that software can differentiate between different revisions of the component. If this field is increased, PMIIDR.Revision should be set to 0b0000. Arm recommends this field matches the PMPIDR2.REVISION field, if present. This field has an IMPLEMENTATION DEFINED value. RO Revision 15 12 15:12 Component minor revision. PMIIDR.Variant and PMIIDR.Revision together form the revision number of the component, with this field being the least significant part. When a component is changed, PMIIDR.Variant or PMIIDR.Revision is increased to ensure that software can differentiate between different revisions of the component. If PMIIDR.Variant field is increased, this field should be set to 0b0000, otherwise the value in this field should be increased. Arm recommends this field matches the PMPIDR3.REVAND field, if present. This field has an IMPLEMENTATION DEFINED value. RO Implementer 11 0 11:0 Contains the JEP106 manufacturer's identification code of the designer of the PMU. The code identifies the designer of the component, which might not be the same as the implementer of the device containing the component. Zero is not a valid JEP106 identification code, meaning a value of zero for PMIIDR indicates this register is not implemented. For an implementation designed by Arm, this field reads as 0x43B. Bits [11:8] contain the JEP106 bank identifier of the designer minus 1. Bit 7 is RES0. Bits [6:0] contain bits [6:0] of the JEP106 manufacturer's identification code of the designer. If PMPIDR4 is implemented, PMPIDR4.DES_2 matches bits [11:8] of this field. If PMPIDR2 is implemented, PMPIDR2.DES_1 matches bits [6:4] of this field. If PMPIDR1 is implemented, PMPIDR1.DES_0 matches bits [3:0] of this field. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_PMUv3_EXT64 is implemented Accessible at offset 0xE08 from PMU When FEAT_PMUv3_EXT is implemented 2026-03-26 20:27:25 2026-03_rel