PMITCTRL Performance Monitors Integration mode Control register PMU when FEAT_PMUv3_EXT is implemented, FEAT_PMUv3 is implemented, and an implementation implements PMITCTRL PMU 0xF00 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW Enables the Performance Monitors to switch from default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection. PMU PMITCTRL is a 32-bit register. 31 1 31:1 Reserved, RES0. IME 0 0 0 Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0b0 Normal operation. 0b1 Integration mode enabled. The following resets apply: If the register is implemented in the Core power domain: On a Cold reset, this field resets to 0. On an External debug reset, the value of this field is unchanged. On a Warm reset, the value of this field is unchanged. If the register is implemented in the External debug power domain: On a Cold reset, the value of this field is unchanged. On an External debug reset, this field resets to 0. On a Warm reset, the value of this field is unchanged. Accessible at offset 0xF00 from PMU 2026-03-26 20:27:25 2026-03_rel