PMLAR Performance Monitors Lock Access Register PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0xFB0 When FEAT_DoPD is implemented and !IsCorePowered() ERROR WO Allows or disallows access to the Performance Monitors registers through a memory-mapped interface. The optional Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage. PMU If FEAT_DoPD is implemented, Software Lock is not implemented by the architecturally-defined debug components of the PE in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain. Software uses PMLAR to set or clear the lock, and PMLSR to check the current status of the lock. PMLAR is a 32-bit register. When PMU Software Lock is implemented KEY 31 0 31:0 Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock, enabling write accesses to this component's registers through a memory-mapped interface. Writing any other value to this register locks the lock, disabling write accesses to this component's registers through a memory mapped interface. Otherwise Otherwise 31 0 31:0 Reserved, RES0. When PMU Software Lock is implemented Accessible at offset 0xFB0 from PMU 2026-03-26 20:27:25 2026-03_rel