PMMIR
Performance Monitors Machine Identification Register
PMU
when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p4 is implemented
PMU
0xE40
When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc)
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0xE40
When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc)
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMMIR
Architectural
AArch32
31
0
31
0
31
0
31
0
PMMIR_EL1
Architectural
AArch64
31
0
31
0
31
0
31
0
PMMIR_EL1
Architectural
AArch64
63
0
63
0
63
0
63
0
when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented
Describes Performance Monitors parameters specific to the implementation.
PMU
PMMIR is in the Core power domain.
PMMIR is a:
64-bit register when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented
32-bit register otherwise
When FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented
63
29
63:29
Reserved, RES0.
SME
28
28
28
PMUv3 for SME. Adds support for the Streaming SVE mode filter.
All other values are reserved.
FEAT_PMUv3_SME implements the functionality identified by the value 1.
0b0
Streaming SVE mode filter not implemented.
0b1
Adds support for the Streaming SVE mode filter.
RO
EDGE
27
24
27:24
PMU event edge detection. With PMMIR_EL1.THWIDTH, indicates implementation of event counter thresholding features.
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, the only permitted value is 0b0000.
FEAT_PMUv3_EDGE implements the functionality identified by the value 0b0001.
FEAT_PMUv3_TH2 implements the functionality identified by the value 0b0010.
0b0000
FEAT_PMUv3_EDGE is not implemented.
0b0001
FEAT_PMUv3_EDGE is implemented.
0b0010
As 0b0001, and adds support for threshold value linking between a pair of counters.
RO
THWIDTH
23
20
23:20
PMEVTYPER<n>_EL0.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVTYPER<n>_EL0.TH field.
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, this field is zero.
Otherwise, the largest value that can be written to PMEVTYPER<n>_EL0.TH is 2(PMMIR.THWIDTH) minus one.
0b0000
FEAT_PMUv3_TH is not implemented.
0b0001
1 bit. PMEVTYPER<n>_EL0.TH[11:1] are RES0.
0b0010
2 bits. PMEVTYPER<n>_EL0.TH[11:2] are RES0.
0b0011
3 bits. PMEVTYPER<n>_EL0.TH[11:3] are RES0.
0b0100
4 bits. PMEVTYPER<n>_EL0.TH[11:4] are RES0.
0b0101
5 bits. PMEVTYPER<n>_EL0.TH[11:5] are RES0.
0b0110
6 bits. PMEVTYPER<n>_EL0.TH[11:6] are RES0.
0b0111
7 bits. PMEVTYPER<n>_EL0.TH[11:7] are RES0.
0b1000
8 bits. PMEVTYPER<n>_EL0.TH[11:8] are RES0.
0b1001
9 bits. PMEVTYPER<n>_EL0.TH[11:9] are RES0.
0b1010
10 bits. PMEVTYPER<n>_EL0.TH[11:10] are RES0.
0b1011
11 bits. PMEVTYPER<n>_EL0.TH[11] is RES0.
0b1100
12 bits.
RO
BUS_WIDTH
19
16
19:16
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
0b0000
The information is not available.
0b0011
Four bytes.
0b0100
8 bytes.
0b0101
16 bytes.
0b0110
32 bytes.
0b0111
64 bytes.
0b1000
128 bytes.
0b1001
256 bytes.
0b1010
512 bytes.
0b1011
1024 bytes.
0b1100
2048 bytes.
RO
BUS_SLOTS
15
8
15:8
Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.
When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.
If the bus count information is not available, this field will read as zero.
This field has an IMPLEMENTATION DEFINED value.
RO
SLOTS
7
0
7:0
Operation width. The largest value by which the STALL_SLOT event might increment in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.
This field has an IMPLEMENTATION DEFINED value.
RO
31
29
31:29
Reserved, RES0.
SME
28
28
28
PMUv3 for SME. Adds support for the Streaming SVE mode filter.
All other values are reserved.
FEAT_PMUv3_SME implements the functionality identified by the value 1.
0b0
Streaming SVE mode filter not implemented.
0b1
Adds support for the Streaming SVE mode filter.
RO
EDGE
27
24
27:24
PMU event edge detection. With PMMIR_EL1.THWIDTH, indicates implementation of event counter thresholding features.
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, the only permitted value is 0b0000.
FEAT_PMUv3_EDGE implements the functionality identified by the value 0b0001.
FEAT_PMUv3_TH2 implements the functionality identified by the value 0b0010.
0b0000
FEAT_PMUv3_EDGE is not implemented.
0b0001
FEAT_PMUv3_EDGE is implemented.
0b0010
As 0b0001, and adds support for threshold value linking between a pair of counters.
RO
THWIDTH
23
20
23:20
PMEVTYPER<n>_EL0.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVTYPER<n>_EL0.TH field.
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, this field is zero.
Otherwise, the largest value that can be written to PMEVTYPER<n>_EL0.TH is 2(PMMIR.THWIDTH) minus one.
0b0000
FEAT_PMUv3_TH is not implemented.
0b0001
1 bit. PMEVTYPER<n>_EL0.TH[11:1] are RES0.
0b0010
2 bits. PMEVTYPER<n>_EL0.TH[11:2] are RES0.
0b0011
3 bits. PMEVTYPER<n>_EL0.TH[11:3] are RES0.
0b0100
4 bits. PMEVTYPER<n>_EL0.TH[11:4] are RES0.
0b0101
5 bits. PMEVTYPER<n>_EL0.TH[11:5] are RES0.
0b0110
6 bits. PMEVTYPER<n>_EL0.TH[11:6] are RES0.
0b0111
7 bits. PMEVTYPER<n>_EL0.TH[11:7] are RES0.
0b1000
8 bits. PMEVTYPER<n>_EL0.TH[11:8] are RES0.
0b1001
9 bits. PMEVTYPER<n>_EL0.TH[11:9] are RES0.
0b1010
10 bits. PMEVTYPER<n>_EL0.TH[11:10] are RES0.
0b1011
11 bits. PMEVTYPER<n>_EL0.TH[11] is RES0.
0b1100
12 bits.
RO
BUS_WIDTH
19
16
19:16
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
0b0000
The information is not available.
0b0011
Four bytes.
0b0100
8 bytes.
0b0101
16 bytes.
0b0110
32 bytes.
0b0111
64 bytes.
0b1000
128 bytes.
0b1001
256 bytes.
0b1010
512 bytes.
0b1011
1024 bytes.
0b1100
2048 bytes.
RO
BUS_SLOTS
15
8
15:8
Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.
When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.
If the bus count information is not available, this field will read as zero.
This field has an IMPLEMENTATION DEFINED value.
RO
SLOTS
7
0
7:0
Operation width. The largest value by which the STALL_SLOT event might increment in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.
This field has an IMPLEMENTATION DEFINED value.
RO
When FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented
If the Core power domain is off or in a low-power state, access to this register returns an Error.
[63:0] Accessible at offset 0xE40 from PMU
When FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented
[31:0] Accessible at offset 0xE40 from PMU
When FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented
2026-03-26 20:27:25
2026-03_rel