PMOVS Performance Monitors Overflow Flag Status register PMU when FEAT_PMUv3_EXT64 is implemented and FEAT_PMUv3 is implemented PMU 0xC90 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RW PMOVSSET_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 PMOVSCLR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 PMOVSR Architectural AArch32 31 0 31 0 31 0 31 0 PMOVSSET Architectural AArch32 31 0 31 0 31 0 31 0 The unsigned overflow flags for the Cycle Count Register, PMCCNTR_EL0, and each of the implemented event counters PMEVCNTR<n>. PMU PMOVS is a 64-bit register. 63 33 63:33 Reserved, RES0. F0 32 32 0 PMICNTR_EL0 unsigned overflow flag. 0b0 PMICNTR_EL0 has not overflowed. 0b1 PMICNTR_EL0 has overflowed. '0' When FEAT_PMUv3_ICNTR is implemented 32 32 32 Reserved, RES0. Otherwise C 31 31 31 Cycle counter unsigned overflow flag. PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0]. 0b0 The cycle counter has not overflowed since this bit was last cleared to 0. 0b1 The cycle counter has overflowed since this bit was last cleared to 0. AU AU P<m> 30 0 30:0 Event counter unsigned overflow bit for PMEVCNTR<m>_EL0. If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<m>_EL0[31:0] or unsigned overflow of PMEVCNTR<m>_EL0[63:0]. When FEAT_PMUv3_EXTPMN is implemented, MDCR_EL2.HLP and PMCR_EL0.LP are applicable only for event counters in the second and first range. For more information about event counter ranges, see MDCR_EL2.HPMN. 30 0 0b0 PMEVCNTR<m>_EL0 has not overflowed since this bit was last cleared to 0. 0b1 PMEVCNTR<m>_EL0 has overflowed since this bit was last cleared to 0. AU AU When m >= NUM_PMU_COUNTERS RAZ/WI FEAT_PMUv3_EXTPMN is implemented m >= UInt(EffectiveEPMN()) !IsMostSecureAccess(addrdesc) RAZ/WI RW Accessible at offset 0xC90 from PMU 2026-03-26 20:27:25 2026-03_rel