PMOVSSET_EL0 Performance Monitors Overflow Flag Status Set Register PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0xCC0 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When FEAT_PMUv3_EXT32 is implemented and SoftwareLockStatus(addrdesc) RO RW PMU 0xCC0 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW PMOVSSET_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented PMOVSCLR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented PMOVSSET_EL0 Architectural AArch64 63 32 63 32 63 32 63 32 when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented PMOVSCLR_EL0 Architectural AArch64 63 32 63 32 63 32 63 32 when FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3p9 is implemented PMOVSR Architectural AArch32 31 0 31 0 31 0 31 0 PMOVSSET Architectural AArch32 31 0 31 0 31 0 31 0 Allows software to set the unsigned overflow flags for the following counters to 1: The cycle counter PMCCNTR_EL0. The event counters PMEVCNTR<n>_EL0. When FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. Reading from this register shows the current unsigned overflow flag values. PMU PMOVSSET_EL0 is in the Core power domain. PMOVSSET_EL0 is a: 64-bit register when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented, or FEAT_PMUv3_ICNTR is implemented 32-bit register otherwise When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented, or FEAT_PMUv3_ICNTR is implemented 63 33 63:33 Reserved, RES0. F0 32 32 0 Unsigned overflow flag for PMICNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMICNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMICNTR_EL0. 0b0 PMICNTR_EL0 has not overflowed. 0b1 PMICNTR_EL0 has overflowed. '0' When SoftwareLockStatus(addrdesc) RO W1S When FEAT_PMUv3_ICNTR is implemented 32 32 32 Reserved, RES0. Otherwise C 31 31 31 Unsigned overflow flag for PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMCCNTR_EL0 overflow status. PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0]. 0b0 PMCCNTR_EL0 has not overflowed. 0b1 PMCCNTR_EL0 has overflowed. AU AU When SoftwareLockStatus(addrdesc) RO W1S P<m> 30 0 30:0 Unsigned overflow flag for PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMEVCNTR<m>_EL0 overflow status. If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<m>_EL0[31:0] or unsigned overflow of PMEVCNTR<m>_EL0[63:0]. When FEAT_PMUv3_EXTPMN is implemented, MDCR_EL2.HLP and PMCR_EL0.LP are applicable only for event counters in the second and first range. For more information about event counter ranges, see MDCR_EL2.HPMN. 30 0 0b0 PMEVCNTR<m>_EL0 has not overflowed. 0b1 PMEVCNTR<m>_EL0 has overflowed. AU AU When m >= NUM_PMU_COUNTERS RAZ/WI FEAT_PMUv3_EXTPMN is implemented m >= UInt(EffectiveEPMN()) !IsMostSecureAccess(addrdesc) RAZ/WI When SoftwareLockStatus(addrdesc) RO W1S C 31 31 31 Unsigned overflow flag for PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMCCNTR_EL0 overflow status. PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0]. 0b0 PMCCNTR_EL0 has not overflowed. 0b1 PMCCNTR_EL0 has overflowed. AU AU When SoftwareLockStatus(addrdesc) RO W1S P<m> 30 0 30:0 Unsigned overflow flag for PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMEVCNTR<m>_EL0 overflow status. If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<m>_EL0[31:0] or unsigned overflow of PMEVCNTR<m>_EL0[63:0]. When FEAT_PMUv3_EXTPMN is implemented, MDCR_EL2.HLP and PMCR_EL0.LP are applicable only for event counters in the second and first range. For more information about event counter ranges, see MDCR_EL2.HPMN. 30 0 0b0 PMEVCNTR<m>_EL0 has not overflowed. 0b1 PMEVCNTR<m>_EL0 has overflowed. AU AU When m >= NUM_PMU_COUNTERS RAZ/WI FEAT_PMUv3_EXTPMN is implemented m >= UInt(EffectiveEPMN()) !IsMostSecureAccess(addrdesc) RAZ/WI When SoftwareLockStatus(addrdesc) RO W1S When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented, or FEAT_PMUv3_ICNTR is implemented [63:0] Accessible at offset 0xCC0 from PMU When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3_ICNTR is implemented, or FEAT_PMUv3p9 is implemented [31:0] Accessible at offset 0xCC0 from PMU When FEAT_PMUv3_EXT32 is implemented, FEAT_PMUv3_ICNTR is not implemented, and FEAT_PMUv3p9 is not implemented 2026-03-26 20:27:25 2026-03_rel