PMPCSR
Program Counter Sample Register
PMU
when FEAT_PMUv3_EXT is implemented and FEAT_PCSRv8p2 is implemented
PMU
0x200
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0x200
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0x204
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0x220
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0x220
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PMU
0x224
When DoubleLockStatus() or !IsCorePowered()
ERROR
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus()
ERROR
RO
PC Sample-based Profiling Extension register that holds a sampled instruction address value.
PMU
PMPCSR is in the Core power domain.
If FEAT_PMUv3_EXT32 is implemented, support for 64-bit atomic reads is IMPLEMENTATION DEFINED. If 64-bit atomic reads are implemented, a 64-bit read of PMPCSR has the same side-effect as a 32-bit read of PMCSR[31:0] followed by a 32-bit read of PMPCSR[63:32], returning the combined value. For example, if the PE is in Debug state, then a 64-bit atomic read returns bits[31:0] == 0xFFFFFFFF and bits[63:32] UNKNOWN.
PMPCSR is a 64-bit register.
NS
63
63
0
Together with the NSE field, indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
When FEAT_RME is implemented
NS
63
63
0
Non-secure state sample. Indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.
0b0
Sample is from Secure state.
0b1
Sample is from Non-secure state.
AU
Otherwise
EL
62
61
62:61
Exception level status sample. Indicates the Exception level that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
0b00
Sample is from EL0.
0b01
Sample is from EL1.
0b10
Sample is from EL2.
0b11
Sample is from EL3.
AU
60
60
60
Reserved, RES0.
NSE
59
59
0
Together with the NS field, indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
For a description of the values derived by evaluating NS and NSE together, see PMPCSR.NS.
When FEAT_RME is implemented
59
59
59
Reserved, RES0.
Otherwise
58
56
58:56
Reserved, RES0.
PCSample[55:32]
55
32
55:32
Bits[55:32] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
AU
PCSample[31:0]
31
0
31:0
Bits[31:0] of the sampled instruction address value.
PMPCSR[31:0] reads as 0xFFFFFFFF when any of the following are true:
The PE is in Debug state.
PC Sample-based profiling is prohibited.
If a branch instruction has retired since the PE left reset state, then the first read of PMPCSR[31:0] is permitted but not required to return 0xFFFFFFFF.
PMPCSR[31:0] reads as an UNKNOWN value when any of the following are true:
The PE is in reset state.
No branch instruction has retired since the PE left reset state, Debug state, or a state where PC Sample-based Profiling is prohibited.
No branch instruction has retired since the last read of PMPCSR[31:0].
For the cases where a read of PMPCSR[31:0] returns 0xFFFFFFFF or an UNKNOWN value, the read has the side-effect of setting PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR to UNKNOWN values.
Otherwise, a read of PMPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
For a read of PMPCSR[31:0] from the memory-mapped interface, if PMLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the side-effect of the access does not occur and PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR are unchanged.
AU
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
A 32-bit access to PMPCSR[63:32] does not update the PC sample registers. Only a 64-bit access to PMPCSR[63:0] or a 32-bit access to PMPCSR[31:0] updates the PC sample registers. This includes the value a subsequent 32-bit read of PMPCSR[63:32] will return.
[63:0] Accessible at offset 0x200 from PMU
When FEAT_PMUv3_EXT64 is implemented
[31:0] Accessible at offset 0x200 from PMU
When FEAT_PMUv3_EXT32 is implemented
[63:32] Accessible at offset 0x204 from PMU
When FEAT_PMUv3_EXT32 is implemented
[63:0] Accessible at offset 0x220 from PMU
When FEAT_PMUv3_EXT64 is implemented
[31:0] Accessible at offset 0x220 from PMU
When FEAT_PMUv3_EXT32 is implemented
[63:32] Accessible at offset 0x224 from PMU
When FEAT_PMUv3_EXT32 is implemented
2026-03-26 20:27:25
2026-03_rel