PMSWINC_EL0 Performance Monitors Software Increment Register PMU when FEAT_PMUv3_EXT32 is implemented, FEAT_PMUv3p9 is not implemented, and an implementation implements PMSWINC_EL0 PMU 0xCA0 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) WI WO PMSWINC_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 PMSWINC Architectural AArch32 31 0 31 0 31 0 31 0 Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR'. PMU PMSWINC_EL0 is in the Core power domain. If this register is implemented, use of it is deprecated. If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface. PMSWINC_EL0 is a 32-bit register. 31 31 31 Reserved, RES0. P<m> 30 0 30:0 Event counter software increment bit for PMEVCNTR<m>_EL0. 30 0 0b0 No action. The write to this bit is ignored. 0b1 It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter m. When m >= NUM_PMU_COUNTERS RAZ/WI When SoftwareLockStatus(addrdesc) RAZ/WI WO/RAZ If FEAT_PMUv3p9 or FEAT_PMUv3_EXT64 are implemented, this location is used for accesses to PMZR_EL0. Accessible at offset 0xCA0 from PMU 2026-03-26 20:27:25 2026-03_rel