PMVIDSR VMID Sample Register PMU when FEAT_PMUv3_EXT32 is implemented, FEAT_PCSRv8p2 is implemented, and EL2 is implemented PMU 0x20C When DoubleLockStatus() or !IsCorePowered() ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PC Sample-based Profiling Extension register that contains the sampled VMID value that is captured on reading PMPCSR[31:0]. PMU PMVIDSR is in the Core power domain. PMVIDSR is a 32-bit register. 31 16 31:16 Reserved, RES0. VMID[15:8] 15 8 7:0 Extension to VMID[7:0]. For more information, see VMID[7:0]. AU When FEAT_VMID16 is implemented 15 8 15:8 Reserved, RES0. Otherwise VMID 7 0 7:0 VMID sample. The VMID associated with the most recent PMPCSR sample. When the most recent PMPCSR sample was generated: This field is set to an UNKNOWN value if any of the following apply: EL2 is disabled in the current Security state. The PE is executing at EL2. The PE is executing at EL0, and the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. Otherwise: If EL2 is using AArch64 and either FEAT_VMID16 is not implemented or VTCR_EL2.VS is 1, this field is set to VTTBR_EL2.VMID. If EL2 is using AArch64, FEAT_VMID16 is implemented, and VTCR_EL2.VS is 0, PMVIDSR.VMID[7:0] is set to VTTBR_EL2.VMID[7:0] and PMVIDSR.VMID[15:8] is RES0. If EL2 is using AArch32, this field is set to VTTBR.VMID. Because the value written to PMVIDSR is an indirect read of the VMID value, it is CONSTRAINED UNPREDICTABLE whether PMVIDSR is set to the original or new value if PMPCSR samples: An instruction that writes to the VMID value. The next Context synchronization event. Any instruction executed between these two instructions. AU If FEAT_PMUv3_EXT64 is implemented, then the same content is present in the same location, and can be accessed using PMVCIDSR[63:32]. IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'. Accessible at offset 0x20C from PMU 2026-03-26 20:27:25 2026-03_rel