This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

ARM Machine Readable Schema - 2.8

AARCHMRS Schema 2.8

2.7

Highlights

Version 2.7.5 introduces additive changes to the schema only. These updates extend the existing schema with new fields and definitions and do not modify or remove any existing schema elements.

AARCHMRS-5227: Update ASL1 implication and logical equivalence syntax

The syntax of the implication and logical equivalence has been updated in the BinaryOp schema to align with the latest ASL reference documentation as the following:

For more details refer to Chapter 3 of ASLRef BET0.

AARCHMRS-5226: Change AST.Concat into an AST.BinaryOp operator (::)

In order to align more closely with the ASL Reference manual we have updated bit concatenation to an AST.BinaryOp operator.

AST.Concat will remain in use when specifying mulit-bit field accesses of the form REG.[F1,F2] and is planned for deprecation in a future version when a better model is made available.