{ "Header": { "Copyright": "Copyright (c) 2022 - 2025 Intel Corporation. All rights reserved.", "Info": "TDX Module Interface functions Completion Status", "Version": "2.0" }, "Operand IDs": [ { "Operand ID": "0", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RAX", "Description": [ "Explicit input operand RAX" ] }, { "Operand ID": "1", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RCX", "Description": [ "Explicit input operand RCX" ] }, { "Operand ID": "2", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RDX", "Description": [ "Explicit input operand RDX" ] }, { "Operand ID": "3", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RBX", "Description": [ "Explicit input operand RBX" ] }, { "Operand ID": "5", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RBP", "Description": [ "Explicit input operand RBP" ] }, { "Operand ID": "6", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RSI", "Description": [ "Explicit input operand RSI" ] }, { "Operand ID": "7", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "RDI", "Description": [ "Explicit input operand RDI" ] }, { "Operand ID": "8", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R8", "Description": [ "Explicit input operand R8" ] }, { "Operand ID": "9", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R9", "Description": [ "Explicit input operand R9" ] }, { "Operand ID": "10", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R10", "Description": [ "Explicit input operand R10" ] }, { "Operand ID": "11", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R11", "Description": [ "Explicit input operand R11" ] }, { "Operand ID": "12", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R12", "Description": [ "Explicit input operand R12" ] }, { "Operand ID": "13", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R13", "Description": [ "Explicit input operand R13" ] }, { "Operand ID": "14", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R14", "Description": [ "Explicit input operand R14" ] }, { "Operand ID": "15", "Explicit/Implicit": "Explicit", "Class": "GPR", "Operand": "R15", "Description": [ "Explicit input operand R15" ] }, { "Operand ID": "64", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "ATTRIBUTES", "Description": [ "TD_PARAMS.ATTRIBUTES" ] }, { "Operand ID": "65", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "XFAM", "Description": [ "TD_PARAMS.XFAM" ] }, { "Operand ID": "66", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "EXEC_CONTROLS", "Description": [ "TD_PARAMS.CONFIG_FLAGS" ] }, { "Operand ID": "67", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "EPTP_CONTROLS", "Description": [ "TD_PARAMS.EPTP_CONTROLS" ] }, { "Operand ID": "68", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "MAX_VCPUS", "Description": [ "TD_PARAMS.MAX_VCPUS" ] }, { "Operand ID": "69", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "CPUID_CONFIG", "Description": [ "TD_PARAMS.CPUID_CONFIG" ] }, { "Operand ID": "70", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "TSC_FREQUENCY", "Description": [ "TD_PARAMS.TSC_FREQUENCY" ] }, { "Operand ID": "71", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "NUM_L2_VMS", "Description": [ "TD_PARAMS.NUM_L2_VMS" ] }, { "Operand ID": "72", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "IA32_ARCH_CAPABILITIES_CONFIG", "Description": [ "TD_PARAMS.IA32_ARCH_CAPABILITIES_CONFIG" ] }, { "Operand ID": "95", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "PAGE", "Description": [ "PAGE PA array entry" ] }, { "Operand ID": "96", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "TDMR_INFO_PA", "Description": [ "TDMR_INFO_PA array entry" ] }, { "Operand ID": "97", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "GPA_LIST_ENTRY", "Description": [ "GPA_LIST array entry" ] }, { "Operand ID": "98", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "MIG_BUFF_LIST_ENTRY", "Description": [ "Migration buffer list entry" ] }, { "Operand ID": "99", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "NEW_PAGE_LIST_ENTRY", "Description": [ "New page list entry" ] }, { "Operand ID": "100", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "KEYNAME", "Description": [ "KEYREQUEST.KEYNAME" ] }, { "Operand ID": "101", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "TDSIGSTRUCT", "Description": [ "TDSIGSTRUCT header or reserved fields" ] }, { "Operand ID": "102", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "SIGNATURE", "Description": [ "TDSIGSTRUCT.SIGNATURE" ] }, { "Operand ID": "103", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "PAGE_LIST_ENTRY", "Description": [ "Entry of a page list", "Upper 16 bits are the list entry index" ] }, { "Operand ID": "104", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "NRX_DESCRIPTOR", "Description": [ "NRX Descriptor" ] }, { "Operand ID": "105", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "MEM_SCAN_CONTEXT", "Description": [ "Memory scan context" ] }, { "Operand ID": "106", "Explicit/Implicit": "Explicit", "Class": "Component of explicit input", "Operand": "GPA_RANGE_LIST_ENTRY", "Description": [ "Memory scan GPA range list entry" ] }, { "Operand ID": "128", "Explicit/Implicit": "Implicit", "Class": "Physical Page", "Operand": "TDR", "Description": [ "TDR Page" ] }, { "Operand ID": "129", "Explicit/Implicit": "Implicit", "Class": "Physical Page", "Operand": "TDCX", "Description": [ "TDCX Page" ] }, { "Operand ID": "130", "Explicit/Implicit": "Implicit", "Class": "Physical Page", "Operand": "TDVPR", "Description": [ "TDVPR Page" ] }, { "Operand ID": "132", "Explicit/Implicit": "Implicit", "Class": "Physical Page", "Operand": "REG_PAGE", "Description": [ "PT_REG private page" ] }, { "Operand ID": "144", "Explicit/Implicit": "Implicit", "Class": "TD logical control structure", "Operand": "TDCS", "Description": [ "TDCS Logical Structure" ] }, { "Operand ID": "145", "Explicit/Implicit": "Implicit", "Class": "TD logical control structure", "Operand": "TDVPS", "Description": [ "TDVPS Logical Structure" ] }, { "Operand ID": "146", "Explicit/Implicit": "Implicit", "Class": "TD logical control structure", "Operand": "SEPT_TREE", "Description": [ "Secure EPT Tree" ] }, { "Operand ID": "147", "Explicit/Implicit": "Implicit", "Class": "TD logical control structure", "Operand": "SEPT_ENTRY", "Description": [ "Secure EPT Entry" ] }, { "Operand ID": "168", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "RTMR", "Description": [ "TDCS.RTMR" ] }, { "Operand ID": "169", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "TD_EPOCH", "Description": [ "TDCS.TD_EPOCH" ] }, { "Operand ID": "170", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "L2_VAPIC_GPA", "Description": [ "TDVPS.L2_VAPIC_GPA" ] }, { "Operand ID": "171", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "MIGSC", "Description": [ "TDCS.MIGSC_LINK and MIGSC page" ] }, { "Operand ID": "172", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "OP_STATE", "Description": [ "TDCS.OP_STATE" ] }, { "Operand ID": "173", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "MIG", "Description": [ "TDCS Migration Context" ] }, { "Operand ID": "174", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "SERVTD_BINDINGS", "Description": [ "Service TD bindings table" ] }, { "Operand ID": "175", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "PASID_TRK", "Description": [ "PASID tracking information" ] }, { "Operand ID": "176", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "METADATA_FIELD", "Description": [ "Metadata field" ] }, { "Operand ID": "177", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "NUM_VCPUS", "Description": [ "TDCS.NUM_VCPUS" ] }, { "Operand ID": "178", "Explicit/Implicit": "Implicit", "Class": "Component of logical control structure", "Operand": "CPUID_FIXED0_BITMAP", "Description": [ "TDCS.CPUID_FIXED0_BITMAP" ] }, { "Operand ID": "184", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "SYS", "Description": [ "Intel TDX Module" ] }, { "Operand ID": "185", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "TDMR", "Description": [ "TDMR" ] }, { "Operand ID": "186", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "KOT", "Description": [ "KOT" ] }, { "Operand ID": "187", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "KET", "Description": [ "KET" ] }, { "Operand ID": "188", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "WBCACHE", "Description": [ "TDH.PHYMEM.CACHE.WB State" ] }, { "Operand ID": "189", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "NRX", "Description": [ "NRX" ] }, { "Operand ID": "190", "Explicit/Implicit": "Implicit", "Class": "Abstract item", "Operand": "MEM_SCAN_STATE", "Description": [ "Memory scan internal state" ] }, { "Operand ID": "256", "Explicit/Implicit": "Implicit", "Class": "TDX I/O abstract item", "Operand": "PASIDMT", "Description": [ "PASID metadata table" ] }, { "Operand ID": "257", "Explicit/Implicit": "Implicit", "Class": "TDX I/O abstract item", "Operand": "MMIOMT", "Description": [ "MMIO physical page metadata table" ] }, { "Operand ID": "258", "Explicit/Implicit": "Implicit", "Class": "TDX I/O abstract item", "Operand": "SPDMMT", "Description": [ "SPDM metadata table" ] }, { "Operand ID": "320", "Explicit/Implicit": "Implicit", "Class": "Global control structure", "Operand": "DMAR", "Description": [ "Trusted DMA remapping structure" ] } ], "Status Codes": [ { "Status Code (Bits 63:32)": "0x00000000", "Status": "Success", "Name": "TDX_SUCCESS", "DETAILS_L2 (Bits 31:0)": [ "For TDH.VP.ENTER: Exit Reason", "For TDG.VP.ENTER: Exit Reason", "For list operations: Number of problematic sub-operations (e.g., a page in a list not processed due to an incorrect state)." ], "Description": [ "Function completed successfully." ] }, { "Status Code (Bits 63:32)": "0x40000001", "Status": "Non-Recover.", "Name": "TDX_NON_RECOVERABLE_VCPU", "DETAILS_L2 (Bits 31:0)": [ "For TDH.VP.ENTER: Exit Reason" ], "Description": [ "TD exit due to a non-recoverable VCPU state (e.g., triple fault) \u2013 VCPU is disabled" ] }, { "Status Code (Bits 63:32)": "0x60000002", "Status": "Fatal", "Name": "TDX_NON_RECOVERABLE_TD", "DETAILS_L2 (Bits 31:0)": [ "For TDH.VP.ENTER: Exit Reason" ], "Description": [ "TD exit due to a non-recoverable TD state \u2013 TD is disabled" ] }, { "Status Code (Bits 63:32)": "0x80000003", "Status": "Recover. Error", "Name": "TDX_INTERRUPTED_RESUMABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Function operation has been interrupted by an external event, and it may be resumed from the point it was interrupted by calling it again." ] }, { "Status Code (Bits 63:32)": "0x80000004", "Status": "Recover. Error", "Name": "TDX_INTERRUPTED_RESTARTABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Function operation has been interrupted by an external event, and it may be restarted (from its beginning) by calling it again." ] }, { "Status Code (Bits 63:32)": "0x60000005", "Status": "Fatal", "Name": "TDX_NON_RECOVERABLE_TD_NON_ACCESSIBLE", "DETAILS_L2 (Bits 31:0)": [ "For TDH.VP.ENTER: Exit Reason" ], "Description": [ "TD exit due to a fatal TD state (e.g., machine check caused by a memory integrity check error) \u2013 TD is disabled and its private memory can't be accessed." ] }, { "Status Code (Bits 63:32)": "0xC0000006", "Status": "Error", "Name": "TDX_INVALID_RESUMPTION", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Resumed function in invalid, e.g., its operands are different than the last interrupted function." ] }, { "Status Code (Bits 63:32)": "0xE0000007", "Status": "Fatal", "Name": "TDX_NON_RECOVERABLE_TD_WRONG_APIC_MODE", "DETAILS_L2 (Bits 31:0)": [ "TDH.VP.ENTER: Exit Reason" ], "Description": [ "TD is disabled due to host VMM running with wrong local APIC mode, e.g.:", "- Local APIC is disabled.", "- Local APIC is mode is xAPIC and there are more than", " 255 logical processors in the platform." ] }, { "Status Code (Bits 63:32)": "0x80000008", "Status": "Recover. Error", "Name": "TDX_CROSS_TD_FAULT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Fault-like TD exit due to a cross-TD error, i.e., the current TD encountered an error that is related to some other TD." ] }, { "Status Code (Bits 63:32)": "0x90000009", "Status": "Host Recover. Error", "Name": "TDX_CROSS_TD_TRAP", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Trap-like TD exit due to a cross-TD error, i.e., the current TD encountered an error that is related to some other TD." ] }, { "Status Code (Bits 63:32)": "0x6000000A", "Status": "Fatal", "Name": "TDX_NON_RECOVERABLE_TD_CORRUPTED_MD", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TD exit due to a non-recoverable corrupted TD metadata \u2013 TD is disabled" ] }, { "Status Code (Bits 63:32)": "0x8000000B", "Status": "Recover. Error", "Name": "TDX_TDCALL_RATE_LIMIT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A long latency guest-side (TDCALL) interface function was called by the guest at a higher rate then allowed. The host VMM can typically resume the guest (TDH.VP.ENTER)." ] }, { "Status Code (Bits 63:32)": "0x8000000C", "Status": "Recover. Error", "Name": "TDX_INTERRUPTED_LIST_FULL", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Operation was interrupted because the output list is full. The host VMM may resume the operation with an updated output list." ] }, { "Status Code (Bits 63:32)": "0xC0000100", "Status": "Error", "Name": "TDX_OPERAND_INVALID", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Operand is invalid." ] }, { "Status Code (Bits 63:32)": "0xC0000101", "Status": "Error", "Name": "TDX_OPERAND_ADDR_RANGE_ERROR", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Operand address is out of range (e.g., not in a TDMR)." ] }, { "Status Code (Bits 63:32)": "0xC0000102", "Status": "Error", "Name": "TDX_EVENT_FILTER_INVALID", "DETAILS_L2 (Bits 31:0)": [ "Number of the event in the list" ], "Description": [ "EVENT_FILTER provided to TDH.MNG.INIT is invalid." ] }, { "Status Code (Bits 63:32)": "0xC0000103", "Status": "Error", "Name": "TDX_EVENT_FILTER_ORDER_INVALID", "DETAILS_L2 (Bits 31:0)": [ "Number of the event in the list" ], "Description": [ "EVENT_FILTERS provided to TDH.MNG.INIT are not sorted as required." ] }, { "Status Code (Bits 63:32)": "0x80000200", "Status": "Recover. Error", "Name": "TDX_OPERAND_BUSY", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "The operand is busy (e.g., it is locked in Exclusive mode)." ] }, { "Status Code (Bits 63:32)": "0x80000201", "Status": "Recover. Error", "Name": "TDX_PREVIOUS_TLB_EPOCH_BUSY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDH.MEM.TRACK failed because one or more of the TD's VCPUs are running, and their VCPU epoch is the previous TD epoch. " ] }, { "Status Code (Bits 63:32)": "0x80000202", "Status": "Recover. Error", "Name": "TDX_SYS_BUSY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The Intel TDX module (as a whole) is busy." ] }, { "Status Code (Bits 63:32)": "0x80000203", "Status": "Recover. Error", "Name": "TDX_RND_NO_ENTROPY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Random number generation (e.g., RDRAND or RDSEED) failed because the hardware random number generator did not have enough entropy. The caller should retry the operation." ] }, { "Status Code (Bits 63:32)": "0x80000204", "Status": "Recover. Error", "Name": "TDX_OPERAND_BUSY_HOST_PRIORITY", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "For host-side functions: The operand is busy; HOST_PRIORITY has been set - the host VMM should retry the operation until successful to avoid guest being stuck on host priority.", "For guest-side functions: The operand is busy (e.g., it is locked in Exclusive mode) due to host priority." ] }, { "Status Code (Bits 63:32)": "0x90000205", "Status": "Host Recover. Error", "Name": "TDX_HOST_PRIORITY_BUSY_TIMEOUT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Guest TD encountered a resource that has been busy due to host priority for more than the configured timeout. This is typically the result of the host VMM failing to acquire access to some resource and not retrying the operation until successful." ] }, { "Status Code (Bits 63:32)": "0x80000206", "Status": "Recover. Error", "Name": "TDX_INTERRUPTED_BUSY", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Function operation has been interrupted because of a busy operand, and it may be resumed from the point it was interrupted by calling it again." ] }, { "Status Code (Bits 63:32)": "0xC0000300", "Status": "Error", "Name": "TDX_PAGE_METADATA_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Physical page metadata (in PAMT) are incorrect for the requested operation." ] }, { "Status Code (Bits 63:32)": "0x00000301", "Status": "Success", "Name": "TDX_PAGE_ALREADY_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Physical page is already marked as PT_FREE." ] }, { "Status Code (Bits 63:32)": "0xC0000302", "Status": "Error", "Name": "TDX_PAGE_NOT_OWNED_BY_TD", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Physical page PAMT entry's OWNER field does not point to the TD's TDR page." ] }, { "Status Code (Bits 63:32)": "0xC0000303", "Status": "Error", "Name": "TDX_PAGE_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Physical page is not free." ] }, { "Status Code (Bits 63:32)": "0xC0000304", "Status": "Error", "Name": "TDX_HPA_RANGE_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Physical memory range is not free." ] }, { "Status Code (Bits 63:32)": "0xC0000305", "Status": "Error", "Name": "TDX_NO_PAMT_PAGE_PAIR", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "No PAMT page pair exists for the specified 2MB HPA range." ] }, { "Status Code (Bits 63:32)": "0xC0000306", "Status": "Error", "Name": "TDX_PAMT_PAGE_NOT_EMPTY", "DETAILS_L2 (Bits 31:0)": [ "PAMT page index in the PAMT page pair (0 or 1)" ], "Description": [ "PAMT page contains one or more entries that are not free." ] }, { "Status Code (Bits 63:32)": "0x80000307", "Status": "Recover. Error", "Name": "TDX_INTERRUPTED_PAMT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Function operation has been interrupted by missing PAMT page pair. It may be resumed from the point it was interrupted (after adding the PAMT page pair) by calling it again." ] }, { "Status Code (Bits 63:32)": "0x80000308", "Status": "Recover. Error", "Name": "TDX_MISSING_PAMT_PAGE_PAIR", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "PAMT page pair mapping the specified 4KB HPA is missing. The function may be retried after adding the missing PAMT page pair." ] }, { "Status Code (Bits 63:32)": "0xC0000400", "Status": "Error", "Name": "TDX_TD_ASSOCIATED_PAGES_EXIST", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Physical pages associated with the TD exist in memory." ] }, { "Status Code (Bits 63:32)": "0xC0000500", "Status": "Error", "Name": "TDX_SYS_INIT_NOT_PENDING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting TDH.SYS.INIT when not expected." ] }, { "Status Code (Bits 63:32)": "0xC0000502", "Status": "Error", "Name": "TDX_SYS_LP_INIT_NOT_DONE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting non-TDH.SYS.LP.INIT SEAMCALL leaf before TDH.SYS.LP.INIT was done on this LP." ] }, { "Status Code (Bits 63:32)": "0xC0000503", "Status": "Error", "Name": "TDX_SYS_LP_INIT_DONE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting TDH.SYS.LP.INIT when already done on this LP." ] }, { "Status Code (Bits 63:32)": "0xC0000505", "Status": "Error", "Name": "TDX_SYS_NOT_READY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting to execute a non-initialization SEAMCALL function before initialization sequence completed." ] }, { "Status Code (Bits 63:32)": "0xC0000506", "Status": "Error", "Name": "TDX_SYS_SHUTDOWN", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting to execute SEAMCALL when the Intel TDX module is being shut down." ] }, { "Status Code (Bits 63:32)": "0xC0000507", "Status": "Error", "Name": "TDX_SYS_KEY_CONFIG_NOT_PENDING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting TDH.SYS.KEY.CONFIG when it is not pending." ] }, { "Status Code (Bits 63:32)": "0xC0000508", "Status": "Error", "Name": "TDX_SYS_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDX module state is incorrect for the requested operation." ] }, { "Status Code (Bits 63:32)": "0xC0000509", "Status": "Error", "Name": "TDX_SYS_INVALID_HANDOFF", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Handoff data is incorrect for TD-preserving TDX module update." ] }, { "Status Code (Bits 63:32)": "0xC000050A", "Status": "Error", "Name": "TDX_SYS_INCOMPATIBLE_SIGSTRUCT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDX module SIGSTRUCT is incompatible with the current TDX module." ] }, { "Status Code (Bits 63:32)": "0xC000050B", "Status": "Error", "Name": "TDX_SYS_LP_INIT_NOT_PENDING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting TDH.SYS.LP.INIT when it is not pending." ] }, { "Status Code (Bits 63:32)": "0xC000050C", "Status": "Error", "Name": "TDX_SYS_CONFIG_NOT_PENDING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting TDH.SYS.CONFIG when it is not pending." ] }, { "Status Code (Bits 63:32)": "0xC000050D", "Status": "Error", "Name": "TDX_INCOMPATIBLE_SEAM_CAPABILITIES", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The CPU does not support the capabilities, as reported by SEAMOP(CAPABILITIES), required by the TDX module." ] }, { "Status Code (Bits 63:32)": "0xC000050F", "Status": "Error", "Name": "TDX_INCOMPATIBLE_SEAM_FEATURES", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The CPU does not support the features, as reported by SEAMOP(FEATURES), required by the TDX module." ] }, { "Status Code (Bits 63:32)": "0xC0000511", "Status": "Error", "Name": "TDX_CRYPTO_SELF_TEST_FAILED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The TDX module's self-test of its crypto library failed." ] }, { "Status Code (Bits 63:32)": "0x80000512", "Status": "Recover. Error", "Name": "TDX_UPDATE_COMPATIBILITY_SENSITIVE", "DETAILS_L2 (Bits 31:0)": [ "Bits 15:0: Reason", "0: TD Build in progress", "1: Interrupted migration function", "Bits 31:16: Details", "- Number of TD builds in progress, or", "- Number of interrupted migration functions" ], "Description": [ "TDH.SYS.SHUTDOWN detected that there is one or more ongoing flows which may not be compatible with an updated TDX module." ] }, { "Status Code (Bits 63:32)": "0xE0000604", "Status": "Fatal", "Name": "TDX_TD_FATAL", "DETAILS_L2 (Bits 31:0)": [ "Operand ID (0 if default)" ], "Description": [ "TD is in a FATAL error state." ] }, { "Status Code (Bits 63:32)": "0xC0000605", "Status": "Error", "Name": "TDX_TD_NON_DEBUG", "DETAILS_L2 (Bits 31:0)": [ "Operand ID (0 if default)" ], "Description": [ "TD's ATTRIBUTES.DEBUG bit is 0." ] }, { "Status Code (Bits 63:32)": "0xC0000606", "Status": "Error", "Name": "TDX_TDCS_NOT_ALLOCATED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID (0 if default)" ], "Description": [ "TDCS pages have not been allocated" ] }, { "Status Code (Bits 63:32)": "0xC0000607", "Status": "Error", "Name": "TDX_LIFECYCLE_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID (0 if default)" ], "Description": [ "The TD's LIFECYCLE_STATE is incorrect for the required operation." ] }, { "Status Code (Bits 63:32)": "0xC0000608", "Status": "Error", "Name": "TDX_OP_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "OP_STATE value (0 if default)" ], "Description": [ "The TD's OP_STATE is incorrect for the required operation." ] }, { "Status Code (Bits 63:32)": "0xC0000609", "Status": "Error", "Name": "TDX_NO_VCPUS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDH.MR.FINALIZE called when no VCPUs have been initialized." ] }, { "Status Code (Bits 63:32)": "0xC0000610", "Status": "Error", "Name": "TDX_TDCX_NUM_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID (0 if default)" ], "Description": [ "The number of TDCX pages is incorrect." ] }, { "Status Code (Bits 63:32)": "0xC0000621", "Status": "Error", "Name": "TDX_X2APIC_ID_NOT_UNIQUE", "DETAILS_L2 (Bits 31:0)": [ "X2APIC ID" ], "Description": [ "The same virtual x2APIC ID value has been assigned to more than one VCPU." ] }, { "Status Code (Bits 63:32)": "0xC0000622", "Status": "Error", "Name": "TDX_INCOMPATIBLE_MRTD_CONTEXT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Crypto context of MRTD, updated during TD build by TDH.MNG.INIT, TDH.MEM.PAGE.ADD and TDH.MR.EXTEND is incompatible with the current TDX module" ] }, { "Status Code (Bits 63:32)": "0xC0000700", "Status": "Error", "Name": "TDX_VCPU_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "VCPU_STATE" ], "Description": [ "The VCPU state is incorrect for the requested operation.", "The VCPU_STATE values below are provided only for debug, and are subject to change with new TDX module releases.", "0x0: VCPU_UNINITIALIZED", "0x2: VCPU_READY", "0x4: VCPU_ACTIVE", "0x8: VCPU_DISABLED", "0x10: VCPU_IMPORT" ] }, { "Status Code (Bits 63:32)": "0x80000701", "Status": "Recover. Error", "Name": "TDX_VCPU_ASSOCIATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The VCPU is already associated with another LP." ] }, { "Status Code (Bits 63:32)": "0x80000702", "Status": "Recover. Error", "Name": "TDX_VCPU_NOT_ASSOCIATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The VCPU is not associated with the current LP." ] }, { "Status Code (Bits 63:32)": "0xC0000704", "Status": "Error", "Name": "TDX_NO_VALID_VE_INFO", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "There is no valid #VE information." ] }, { "Status Code (Bits 63:32)": "0xC0000705", "Status": "Error", "Name": "TDX_MAX_VCPUS_EXCEEDED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TD's maximum number of VCPUs has been exceeded." ] }, { "Status Code (Bits 63:32)": "0xC0000706", "Status": "Error", "Name": "TDX_TSC_ROLLBACK", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Time Stamp Counter value is lower than on last TD exit." ] }, { "Status Code (Bits 63:32)": "0xC0000707", "Status": "Error", "Name": "TDX_INTERRUPTIBILITY_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "VMCS Interruptibility State field" ], "Description": [ "Guest TD is not interruptible, due to executing an STI, MOV to SS or POP to SS instruction immediately before TDCALL." ] }, { "Status Code (Bits 63:32)": "0xC0000730", "Status": "Error", "Name": "TDX_TD_VMCS_FIELD_NOT_INITIALIZED", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: VMCS field code" ], "Description": [ "The TD VMCS field has not been initialized." ] }, { "Status Code (Bits 63:32)": "0xC0000731", "Status": "Error", "Name": "TD_VMCS_FIELD_ERROR", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: VMCS field code" ], "Description": [ "The TD VMCS field read or write failed." ] }, { "Status Code (Bits 63:32)": "0x80000800", "Status": "Recover. Error", "Name": "TDX_KEY_GENERATION_FAILED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Failed to generate a random key. This is typically caused by an entropy error of the CPU's random number generator, and may be impacted by RDSEED, RDRAND or PCONFIG executing on other LPs. The operation should be retried." ] }, { "Status Code (Bits 63:32)": "0x80000810", "Status": "Recover. Error", "Name": "TDX_TD_KEYS_NOT_CONFIGURED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TD keys have not been configured on the hardware." ] }, { "Status Code (Bits 63:32)": "0xC0000811", "Status": "Error", "Name": "TDX_KEY_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "KOT entry state is incorrect for the required operation." ] }, { "Status Code (Bits 63:32)": "0x00000815", "Status": "Success", "Name": "TDX_KEY_CONFIGURED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The key is already configured on the current package." ] }, { "Status Code (Bits 63:32)": "0x80000817", "Status": "Recover. Error", "Name": "TDX_WBCACHE_NOT_COMPLETE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting to execute TDH.MNG.KEY.FREEID when TDH.PHYMEM.CACHE.WB has not completed its operation." ] }, { "Status Code (Bits 63:32)": "0xC0000820", "Status": "Error", "Name": "TDX_HKID_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A provided HKID cannot be assigned because it is not free." ] }, { "Status Code (Bits 63:32)": "0x00000821", "Status": "Success", "Name": "TDX_NO_HKID_READY_TO_WBCACHE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "No private HKID is in the HKID_FLUSHED state, ready for TDH.PHYMEM.CACHE.WB." ] }, { "Status Code (Bits 63:32)": "0xC0000823", "Status": "Error", "Name": "TDX_WBCACHE_RESUME_ERROR", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Resume of a previously interrupted function has been aborted due to wrong HKID." ] }, { "Status Code (Bits 63:32)": "0x80000824", "Status": "Recover. Error", "Name": "TDX_FLUSHVP_NOT_DONE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDH.VP.FLUSH was not done on all required VCPUs; some VCPUs are still associated with LPs." ] }, { "Status Code (Bits 63:32)": "0xC0000825", "Status": "Error", "Name": "TDX_NUM_ACTIVATED_HKIDS_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: Maximum supported HKIDs" ], "Description": [ "The number of activated key IDs on the platform is not supported." ] }, { "Status Code (Bits 63:32)": "0xC0000900", "Status": "Error", "Name": "TDX_INCORRECT_CPUID_VALUE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A CPUID value is incorrect." ] }, { "Status Code (Bits 63:32)": "0xC0000901", "Status": "Error", "Name": "TDX_LIMIT_CPUID_MAXVAL_SET", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "MSR IA32_MISC_ENABLES bit 22 (Limit CPUID Maxval) is set." ] }, { "Status Code (Bits 63:32)": "0xC0000902", "Status": "Error", "Name": "TDX_INCONSISTENT_CPUID_FIELD", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A field returned by CPUID is inconsistent between LPs." ] }, { "Status Code (Bits 63:32)": "0xC0000903", "Status": "Error", "Name": "TDX_CPUID_MAX_SUBLEAVES_UNRECOGNIZED", "DETAILS_L2 (Bits 31:0)": [ "CPUID leaf" ], "Description": [ "The maximum number of sub-leaves for this CPUID leaf is not recognized." ] }, { "Status Code (Bits 63:32)": "0xC0000904", "Status": "Error", "Name": "TDX_CPUID_LEAF_1F_FORMAT_UNRECOGNIZED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "CPUID leaf 1F format is not recognized or sub-leaves are not in order." ] }, { "Status Code (Bits 63:32)": "0xC0000905", "Status": "Error", "Name": "TDX_INVALID_WBINVD_SCOPE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "WBINVD scope is not supported." ] }, { "Status Code (Bits 63:32)": "0xC0000906", "Status": "Error", "Name": "TDX_INVALID_PKG_ID", "DETAILS_L2 (Bits 31:0)": [ "Package ID" ], "Description": [ "Package ID is larger than the maximum supported." ] }, { "Status Code (Bits 63:32)": "0xC0000907", "Status": "Error", "Name": "TDX_ENABLE_MONITOR_FSM_NOT_SET", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "MSR IA32_MISC_ENABLES bit 3 (Enable Monitor FSM) is not set." ] }, { "Status Code (Bits 63:32)": "0xC0000908", "Status": "Error", "Name": "TDX_CPUID_LEAF_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "CPUID leaf" ], "Description": [ "None" ] }, { "Status Code (Bits 63:32)": "0xC0000910", "Status": "Error", "Name": "TDX_SMRR_NOT_LOCKED", "DETAILS_L2 (Bits 31:0)": [ "0: SMRR, 1: SMRR2" ], "Description": [ "SMRR* is not locked." ] }, { "Status Code (Bits 63:32)": "0xC0000911", "Status": "Error", "Name": "TDX_INVALID_SMRR_CONFIGURATION", "DETAILS_L2 (Bits 31:0)": [ "0: SMRR, 1: SMRR2" ], "Description": [ "SMRR* configuration is invalid." ] }, { "Status Code (Bits 63:32)": "0xC0000912", "Status": "Error", "Name": "TDX_SMRR_OVERLAPS_CMR", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: 0: SMRR, 1: SMRR2", "Bits 15:8: Overlapping CMR index" ], "Description": [ "SMRR* overlaps a CMR." ] }, { "Status Code (Bits 63:32)": "0xC0000913", "Status": "Error", "Name": "TDX_SMRR_LOCK_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Platform does not support SMRR locking." ] }, { "Status Code (Bits 63:32)": "0xC0000914", "Status": "Error", "Name": "TDX_SMRR_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Platform does not support SMRR." ] }, { "Status Code (Bits 63:32)": "0xC0000920", "Status": "Error", "Name": "TDX_INCONSISTENT_MSR", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: MSR index" ], "Description": [ "MSR configuration is inconsistent between LPs." ] }, { "Status Code (Bits 63:32)": "0xC0000921", "Status": "Error", "Name": "TDX_INCORRECT_MSR_VALUE", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: MSR index" ], "Description": [ "MSR value is incorrect." ] }, { "Status Code (Bits 63:32)": "0xC0000930", "Status": "Error", "Name": "TDX_SEAMREPORT_NOT_AVAILABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SEAMOPS(SEAMREPORT) instruction leaf is not available." ] }, { "Status Code (Bits 63:32)": "0xC0000931", "Status": "Error", "Name": "TDX_SEAMDB_GETREF_NOT_AVAILABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SEAMOPS(SEAMDB_GETREF) instruction leaf is not available." ] }, { "Status Code (Bits 63:32)": "0xC0000932", "Status": "Error", "Name": "TDX_SEAMDB_REPORT_NOT_AVAILABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SEAMOPS(SEAMDB_REPORT) instruction leaf is not available." ] }, { "Status Code (Bits 63:32)": "0xC0000933", "Status": "Error", "Name": "TDX_SEAMVERIFYREPORT_NOT_AVAILABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SEAMOPS(SEAMVERIFYREPORT) instruction leaf is not available." ] }, { "Status Code (Bits 63:32)": "0xC0000934", "Status": "Error", "Name": "TDX_UNKNOWN_TDSTATE_ENUM", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SEAMOPS(TDSTATE_ENUM) instruction reported an unknown value." ] }, { "Status Code (Bits 63:32)": "0xC0000A00", "Status": "Error", "Name": "TDX_INVALID_TDMR", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index" ], "Description": [ "TDMR base address is not aligned on 1GB, its HKID bits are not 0, TDMR size is not specified with 1GB granularity or TDMR is outside the platform's maximum PA." ] }, { "Status Code (Bits 63:32)": "0xC0000A01", "Status": "Error", "Name": "TDX_NON_ORDERED_TDMR", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index" ], "Description": [ "TDMR is not specified in an ascending, non-overlapping order." ] }, { "Status Code (Bits 63:32)": "0xC0000A02", "Status": "Error", "Name": "TDX_TDMR_OUTSIDE_CMRS", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index" ], "Description": [ "TDMR non-reserved parts are not fully contained in CMRs." ] }, { "Status Code (Bits 63:32)": "0x00000A03", "Status": "Success", "Name": "TDX_TDMR_ALREADY_INITIALIZED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDMR is already fully initialized." ] }, { "Status Code (Bits 63:32)": "0xC0000A10", "Status": "Error", "Name": "TDX_INVALID_PAMT", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index", "Bits 15:8: PAMT level (2: 1GB,", " 1: 2MB, 0: 4KB)" ], "Description": [ "PAMT region base address is not aligned on 4KB, its HKID bits are not 0, PAMT region size is not specified with 4KB granularity, it is not large enough for the TDMR size or PAMT region is outside the platform's maximum PA." ] }, { "Status Code (Bits 63:32)": "0xC0000A11", "Status": "Error", "Name": "TDX_PAMT_OUTSIDE_CMRS", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index", "Bits 15:8: PAMT level (2: 1GB,", " 1: 2MB, 0: 4KB)" ], "Description": [ "PAMT is not fully contained in CMRs." ] }, { "Status Code (Bits 63:32)": "0xC0000A12", "Status": "Error", "Name": "TDX_PAMT_OVERLAP", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index", "Bits 15:8: PAMT level (2: 1GB,", " 1: 2MB, 0: 4KB)", "Bits 23:16: Overlapping TDMR index" ], "Description": [ "PAMT overlaps with TDMR non-reserved parts or with another PAMT." ] }, { "Status Code (Bits 63:32)": "0xC0000A20", "Status": "Error", "Name": "TDX_INVALID_RESERVED_IN_TDMR", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index", "Bits 15:8: Reserved area index" ], "Description": [ "Reserved area in TMDR's base offset is not aligned on 4KB, its size is not specified with 4KB granularity or it is not fully contained within the TDMR." ] }, { "Status Code (Bits 63:32)": "0xC0000A21", "Status": "Error", "Name": "TDX_NON_ORDERED_RESERVED_IN_TDMR", "DETAILS_L2 (Bits 31:0)": [ "Bits 7:0: TDMR index", "Bits 15:8: Reserved area index" ], "Description": [ "Reserved area in TDMR is not specified in an ascending, non-overlapping order." ] }, { "Status Code (Bits 63:32)": "0xC0000A22", "Status": "Error", "Name": "TDX_CMR_LIST_INVALID", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "CMR list provided to the TDX module is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000B00", "Status": "Error", "Name": "TDX_EPT_WALK_FAILED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT walk failed" ] }, { "Status Code (Bits 63:32)": "0xC0000B01", "Status": "Error", "Name": "TDX_EPT_ENTRY_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry is free" ] }, { "Status Code (Bits 63:32)": "0xC0000B02", "Status": "Error", "Name": "TDX_EPT_ENTRY_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry is not free" ] }, { "Status Code (Bits 63:32)": "0xC0000B03", "Status": "Error", "Name": "TDX_EPT_ENTRY_NOT_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry is not present" ] }, { "Status Code (Bits 63:32)": "0xC0000B04", "Status": "Error", "Name": "TDX_EPT_ENTRY_NOT_LEAF", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry is not a leaf" ] }, { "Status Code (Bits 63:32)": "0xC0000B05", "Status": "Error", "Name": "TDX_EPT_ENTRY_LEAF", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry is a leaf" ] }, { "Status Code (Bits 63:32)": "0xC0000B06", "Status": "Error", "Name": "TDX_GPA_RANGE_NOT_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "GPA range is not blocked" ] }, { "Status Code (Bits 63:32)": "0x00000B07", "Status": "Success", "Name": "TDX_GPA_RANGE_ALREADY_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "GPA range is already blocked" ] }, { "Status Code (Bits 63:32)": "0xC0000B08", "Status": "Error", "Name": "TDX_TLB_TRACKING_NOT_DONE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TLB tracking has not been done" ] }, { "Status Code (Bits 63:32)": "0xC0000B09", "Status": "Error", "Name": "TDX_EPT_INVALID_PROMOTE_CONDITIONS", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Conditions for GPA mapping promotions as invalid" ] }, { "Status Code (Bits 63:32)": "0x00000B0A", "Status": "Success", "Name": "TDX_PAGE_ALREADY_ACCEPTED", "DETAILS_L2 (Bits 31:0)": [ "Error EPT level" ], "Description": [ "Page has already been accepted" ] }, { "Status Code (Bits 63:32)": "0xC0000B0B", "Status": "Error", "Name": "TDX_PAGE_SIZE_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "Error EPT level" ], "Description": [ "Requested page size does not match the current GPA mapping size" ] }, { "Status Code (Bits 63:32)": "0xC0000B0C", "Status": "Error", "Name": "TDX_GPA_RANGE_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "GPA range is blocked" ] }, { "Status Code (Bits 63:32)": "0xC0000B0D", "Status": "Error", "Name": "TDX_EPT_ENTRY_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT entry state is incorrect" ] }, { "Status Code (Bits 63:32)": "0xC0000B0E", "Status": "Error", "Name": "TDX_EPT_PAGE_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "EPT page is not free" ] }, { "Status Code (Bits 63:32)": "0xC0000B0F", "Status": "Error", "Name": "TDX_L2_SEPT_WALK_FAILED", "DETAILS_L2 (Bits 31:0)": [ "Bits 15:0: Error EPT level", "Bits 31:16: VM index" ], "Description": [ "L2 Secure EPT walk failed" ] }, { "Status Code (Bits 63:32)": "0xC0000B10", "Status": "Error", "Name": "TDX_L2_SEPT_ENTRY_NOT_FREE", "DETAILS_L2 (Bits 31:0)": [ "Bits 15:0: Error EPT level", "Bits 31:16: VM index" ], "Description": [ "L2 Secure EPT entry is not free" ] }, { "Status Code (Bits 63:32)": "0xC0000B11", "Status": "Error", "Name": "TDX_PAGE_ATTR_INVALID", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "The attributes combination requested for a page is invalid." ] }, { "Status Code (Bits 63:32)": "0xC0000B12", "Status": "Error", "Name": "TDX_L2_SEPT_PAGE_NOT_PROVIDED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "On TDH.MEM.PAGE.DEMOTE, a new L2 SEPT page was not provided but a page alias exists." ] }, { "Status Code (Bits 63:32)": "0x80000B13", "Status": "Recover. Error", "Name": "TDX_BLOCKED_MEMORY_EXISTS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Operation failed because some of the TD's private memory is blocked. The host VMM may read BLOCKED_COUNT and PENDING_BLOCKED_COUNT using TDH.MNG.RD. The host VMM may retry the operation when no more memory is blocked." ] }, { "Status Code (Bits 63:32)": "0xC0000C00", "Status": "Error", "Name": "TDX_METADATA_FIELD_ID_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "The provided FIELD_ID is incorrect." ] }, { "Status Code (Bits 63:32)": "0xC0000C01", "Status": "Error", "Name": "TDX_METADATA_FIELD_NOT_WRITABLE", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "Field code and write mask are for a read-only field." ] }, { "Status Code (Bits 63:32)": "0xC0000C02", "Status": "Error", "Name": "TDX_METADATA_FIELD_NOT_READABLE", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "Field code is for an unreadable field." ] }, { "Status Code (Bits 63:32)": "0xC0000C03", "Status": "Error", "Name": "TDX_METADATA_FIELD_VALUE_NOT_VALID", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "The provided field value is not valid." ] }, { "Status Code (Bits 63:32)": "0xC0000C04", "Status": "Error", "Name": "TDX_METADATA_LIST_OVERFLOW", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "A metadata list does not fit within the provided buffer" ] }, { "Status Code (Bits 63:32)": "0xC0000C05", "Status": "Error", "Name": "TDX_INVALID_METADATA_LIST_HEADER", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Metadata list header is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000C06", "Status": "Error", "Name": "TDX_REQUIRED_METADATA_FIELD_MISSING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A required metadata field is missing" ] }, { "Status Code (Bits 63:32)": "0xC0000C07", "Status": "Error", "Name": "TDX_METADATA_ELEMENT_SIZE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "A metadata field identifier specifies an incorrect ELEMENT_SIZE_CODE for the field" ] }, { "Status Code (Bits 63:32)": "0xC0000C08", "Status": "Error", "Name": "TDX_METADATA_LAST_ELEMENT_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "A metadata field identifier specifies an incorrect LAST_ELEMENT_IN_FIELD for the field" ] }, { "Status Code (Bits 63:32)": "0xC0000C09", "Status": "Error", "Name": "TDX_METADATA_FIELD_CURRENTLY_NOT_WRITABLE", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "The metadata field is currently not writable, e.g., per some state of the TD" ] }, { "Status Code (Bits 63:32)": "0xC0000C0A", "Status": "Error", "Name": "TDX_METADATA_WR_MASK_NOT_VALID", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "The write mask value is not valid for the metadata field" ] }, { "Status Code (Bits 63:32)": "0x00000C0B", "Status": "Success", "Name": "TDX_METADATA_FIRST_FIELD_ID_IN_CONTEXT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Indicates that the first accessible field ID in context is returned" ] }, { "Status Code (Bits 63:32)": "0x00000C0C", "Status": "Success", "Name": "TDX_METADATA_FIELD_SKIP", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Indicates that the field value being read is not applicable and needs to be skipped." ] }, { "Status Code (Bits 63:32)": "0xC0000C0D", "Status": "Error", "Name": "TDX_VIRTUAL_MSR_VALUE_NOT_VALID", "DETAILS_L2 (Bits 31:0)": [ "Bits 31:0: MSR Index" ], "Description": [ "Virtual MSR value is incorrect" ] }, { "Status Code (Bits 63:32)": "0xC0000C0E", "Status": "Error", "Name": "TDX_METADATA_FIELD_NOT_ALLOCATED", "DETAILS_L2 (Bits 31:0)": [ "For a single field, set to 0.", "For a metadata list:", "Bits 15:0: Sequence number", " 0xFFFF indicates the list header.", "Bits 31:16: Field number in sequence", " 0xFFFF indicates the sequence", " header." ], "Description": [ "The applicable structure allocated in memory has no place to hold the metadata field " ] }, { "Status Code (Bits 63:32)": "0xC0000D00", "Status": "Error", "Name": "TDX_SERVTD_ALREADY_BOUND_FOR_TYPE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A single service TD of this type is supported" ] }, { "Status Code (Bits 63:32)": "0xC0000D01", "Status": "Error", "Name": "TDX_SERVTD_TYPE_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Service TD type does not match the currently bound type" ] }, { "Status Code (Bits 63:32)": "0xC0000D02", "Status": "Error", "Name": "TDX_SERVTD_ATTR_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Service TD attributes do not match the currently bound attributes" ] }, { "Status Code (Bits 63:32)": "0xC0000D03", "Status": "Error", "Name": "TDX_SERVTD_INFO_HASH_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Service TD hash of TDINFO_STRUCT does not match the currently bound hash" ] }, { "Status Code (Bits 63:32)": "0xC0000D04", "Status": "Error", "Name": "TDX_SERVTD_UUID_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Service TD UUID does not match the currently bound UUID" ] }, { "Status Code (Bits 63:32)": "0xC0000D05", "Status": "Error", "Name": "TDX_SERVTD_NOT_BOUND", "DETAILS_L2 (Bits 31:0)": [ "Binding slot number" ], "Description": [ "Service TD is not bound" ] }, { "Status Code (Bits 63:32)": "0xC0000D06", "Status": "Error", "Name": "TDX_SERVTD_BOUND", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Service TD is already bound" ] }, { "Status Code (Bits 63:32)": "0xC0000D07", "Status": "Error", "Name": "TDX_TARGET_UUID_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Target TD UUID does not match the requested TD_UUID" ] }, { "Status Code (Bits 63:32)": "0xC0000D08", "Status": "Error", "Name": "TDX_TARGET_UUID_UPDATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Target TD UUID does not match the requested TD_UUID, but pre-migration target TD UUID does match it" ] }, { "Status Code (Bits 63:32)": "0x80000D09", "Status": "Recover. Error", "Name": "TDX_REBIND_TOKEN_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Target TD rebind session token does not match the accepted rebind session token of the new service TD" ] }, { "Status Code (Bits 63:32)": "0x80000D0A", "Status": "Recover. Error", "Name": "TDX_REBIND_SERVTD_EXT_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Target TD calculated SERVTD_EXT hash does not match the rebind SERVTD_EXT hash accepted by the new service TD" ] }, { "Status Code (Bits 63:32)": "0x80000D0B", "Status": "Recover. Error", "Name": "TDX_SERVTD_INCORRECT_BINDING_STATE", "DETAILS_L2 (Bits 31:0)": [ "Binding State" ], "Description": [ "Target TD binding state is not in the expected state" ] }, { "Status Code (Bits 63:32)": "0xC0000E00", "Status": "Error", "Name": "TDX_INVALID_MBMD", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "MBMD is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000E01", "Status": "Error", "Name": "TDX_INCORRECT_MBMD_MAC", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "MBMD.MAC field value is incorrect" ] }, { "Status Code (Bits 63:32)": "0xC0000E02", "Status": "Error", "Name": "TDX_NOT_WRITE_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Secure EPT entry is not blocked for writing" ] }, { "Status Code (Bits 63:32)": "0x00000E03", "Status": "Success", "Name": "TDX_ALREADY_WRITE_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Secure EPT entry is already blocked for writing" ] }, { "Status Code (Bits 63:32)": "0xC0000E04", "Status": "Error", "Name": "TDX_NOT_EXPORTED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Secure EPT entry is not marked as exported" ] }, { "Status Code (Bits 63:32)": "0xC0000E05", "Status": "Error", "Name": "TDX_MIGRATION_STREAM_STATE_INCORRECT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Migration stream has not been initialized or is not enabled" ] }, { "Status Code (Bits 63:32)": "0xC0000E06", "Status": "Error", "Name": "TDX_MAX_MIGS_NUM_EXCEEDED", "DETAILS_L2 (Bits 31:0)": [ "MAX_MIGS" ], "Description": [ "The maximum number of supported migration streams has been exceeded" ] }, { "Status Code (Bits 63:32)": "0xC0000E07", "Status": "Error", "Name": "TDX_EXPORTED_DIRTY_PAGES_REMAIN", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "There are some pages that have been exported, but need to be re-exported because their contents have changed" ] }, { "Status Code (Bits 63:32)": "0xC0000E08", "Status": "Error", "Name": "TDX_MIGRATION_DECRYPTION_KEY_NOT_SET", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A new migration decryption key has not been set before a migration session start is attempted" ] }, { "Status Code (Bits 63:32)": "0xC0000E09", "Status": "Error", "Name": "TDX_TD_NOT_MIGRATABLE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The TD's ATTRIBUTES.MIGRATABLE bit is not set" ] }, { "Status Code (Bits 63:32)": "0xC0000E0A", "Status": "Error", "Name": "TDX_PREVIOUS_EXPORT_CLEANUP_INCOMPLETE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A previous aborted export session cleanup (using TDH.EXPORT.CANCEL) has not been completed" ] }, { "Status Code (Bits 63:32)": "0xC0000E0B", "Status": "Error", "Name": "TDX_NUM_MIGS_HIGHER_THAN_CREATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The number of migration streams used by the session is higher than the number of created migration streams" ] }, { "Status Code (Bits 63:32)": "0xC0000E0C", "Status": "Error", "Name": "TDX_IMPORT_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A re-import or an import cancellation does not match the existing Secure EPT entry" ] }, { "Status Code (Bits 63:32)": "0xC0000E0D", "Status": "Error", "Name": "TDX_MIGRATION_EPOCH_OVERFLOW", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Migration epoch has exceeded its maximum value" ] }, { "Status Code (Bits 63:32)": "0xC0000E0E", "Status": "Error", "Name": "TDX_MAX_EXPORTS_EXCEEDED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Maximum number of TD export attempts (2^31) has been exceeded" ] }, { "Status Code (Bits 63:32)": "0xC0000E0F", "Status": "Error", "Name": "TDX_INVALID_PAGE_MAC", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Imported page MAC is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000E10", "Status": "Error", "Name": "TDX_MIGRATED_IN_CURRENT_EPOCH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Page already migrated in the current epoch" ] }, { "Status Code (Bits 63:32)": "0xC0000E11", "Status": "Error", "Name": "TDX_DISALLOWED_IMPORT_OVER_REMOVED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Disallowed age import over a previously-removed page" ] }, { "Status Code (Bits 63:32)": "0xC0000E12", "Status": "Error", "Name": "TDX_SOME_VCPUS_NOT_MIGRATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Some VCPUs have not been migrated" ] }, { "Status Code (Bits 63:32)": "0xC0000E13", "Status": "Error", "Name": "TDX_ALL_VCPUS_IMPORTED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Attempting to import a VCPU when all VCPUs have already been imported" ] }, { "Status Code (Bits 63:32)": "0xC0000E14", "Status": "Error", "Name": "TDX_MIN_MIGS_NOT_CREATED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The minimum number of migration streams (2) to support migration has not been created." ] }, { "Status Code (Bits 63:32)": "0xC0000E15", "Status": "Error", "Name": "TDX_VCPU_ALREADY_EXPORTED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The VCPU has already been exported in the current export session" ] }, { "Status Code (Bits 63:32)": "0xC0000E16", "Status": "Error", "Name": "TDX_INVALID_MIGRATION_DECRYPTION_KEY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The migration decryption key is the same as a previous key or is 0" ] }, { "Status Code (Bits 63:32)": "0x00000E17", "Status": "Success", "Name": "TDX_MEM_RANGE_SCAN_SUCCESS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Comprehensive scan of the current GPA range completed successfully" ] }, { "Status Code (Bits 63:32)": "0x00000E18", "Status": "Success", "Name": "TDX_MEM_SCAN_SUCCESS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Comprehensive scan of the whole TD private GPA address space completed successfully" ] }, { "Status Code (Bits 63:32)": "0x80000E19", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_FAILED_BLOCKED_RANGE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The comprehensive GPA space scan failed because a blocked memory range was detected" ] }, { "Status Code (Bits 63:32)": "0x80000E1A", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_FAILED_OTHER_THREAD", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A comprehensive GPA space scan failure was detected by TDH.MEM.SCAN running on another thread" ] }, { "Status Code (Bits 63:32)": "0x80000E1B", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_CONFIG_REQUIRED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Comprehensive GPA space scan has not been configured by TDH.COMP.SCAN.CONFIG" ] }, { "Status Code (Bits 63:32)": "0x80000E1C", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_RESET_REQUIRED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The comprehensive GPA space scan state needs to be reset after a previous scan, by calling TDH.COMP.SCAN.RESET" ] }, { "Status Code (Bits 63:32)": "0x80000E1D", "Status": "Recover. Error", "Name": "TDX_UNEXPORTED_MEMORY_REMAINS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Operation failed because some of the TD's private memory has not been exported. The host VMM may read MEM_COUNT and MIG_COUNT using TDH.MNG.RD. The host VMM may export the remaining memory and retry the operation." ] }, { "Status Code (Bits 63:32)": "0xC0000E1E", "Status": "Error", "Name": "TDX_MEM_SCAN_CONFIG_ALREADY_DONE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Comprehensive GPA space scan has already been configured by TDH.COMP.SCAN.CONFIG" ] }, { "Status Code (Bits 63:32)": "0x80000E1F", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_IN_PROGRESS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Comprehensive GPA space scan is in progress" ] }, { "Status Code (Bits 63:32)": "0xC0000E20", "Status": "Error", "Name": "TDX_BLOCKING_DISALLOWED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Memory blocking is not allowed" ] }, { "Status Code (Bits 63:32)": "0x80000E21", "Status": "Recover. Error", "Name": "TDX_MEM_SCAN_DCHECK_NOT_DONE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A comprehensive GPA space scan by TDH.COMP.SCAN.COMP(DCHECK) has not coompleted successfully for this export session" ] }, { "Status Code (Bits 63:32)": "0xC0000E22", "Status": "Error", "Name": "TDX_INCOMPATIBLE_MBMD_MAC_CONTEXT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Crypto context saved when the migration function was interrupted is incompatible with the current TDX module" ] }, { "Status Code (Bits 63:32)": "0xC0000F00", "Status": "Error", "Name": "TDX_IOMMU_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IOMMU state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F01", "Status": "Error", "Name": "TDX_IOMMU_IQ_QUEUE_FULL", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IOMMU invalidation queue is full" ] }, { "Status Code (Bits 63:32)": "0xC0000F02", "Status": "Error", "Name": "TDX_IOMMU_RP_NOT_CONFIGURED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Root port is not configured" ] }, { "Status Code (Bits 63:32)": "0xC0000F03", "Status": "Error", "Name": "TDX_IOMMU_IOTLB_TRACKING_NOT_DONE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IOMMU IOTBL tracking is not done" ] }, { "Status Code (Bits 63:32)": "0xC0000F04", "Status": "Error", "Name": "TDX_IOMMU_RP_IDE_MUST_BE_DISABLED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Root port configuration failed because IDE must be disabled" ] }, { "Status Code (Bits 63:32)": "0xC0000F05", "Status": "Error", "Name": "TDX_SPDM_HAS_ACTIVE_IDE_STREAMS", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "SPMD sessions has associated active IDE streams " ] }, { "Status Code (Bits 63:32)": "0xC0000F06", "Status": "Error", "Name": "TDX_SPDM_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "SPDM state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F07", "Status": "Error", "Name": "TDX_DMAR_INVALID_MAPPING_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DMAR mapping state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F08", "Status": "Error", "Name": "TDX_DMAR_INVALID_INV_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DMAR invalidation state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F0B", "Status": "Error", "Name": "TDX_TDI_PKH_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI public key hash mismatch " ] }, { "Status Code (Bits 63:32)": "0xC0000F0F", "Status": "Error", "Name": "TDX_TDI_TDISP_INVALID_MESSAGE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DIMP request/response has an invalid or unsupported format" ] }, { "Status Code (Bits 63:32)": "0xC0000F10", "Status": "Error", "Name": "TDX_TDI_TDISP_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DIMP state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F11", "Status": "Error", "Name": "TDX_TDI_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI state is not valid for the operation" ] }, { "Status Code (Bits 63:32)": "0xC0000F13", "Status": "Error", "Name": "TDX_TDI_HAS_MAPPED_MMIO", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI has mapped MMIO pages" ] }, { "Status Code (Bits 63:32)": "0xC0000F17", "Status": "Error", "Name": "TDX_IDE_STREAM_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE streams not supported by this platfrom" ] }, { "Status Code (Bits 63:32)": "0xC0000F18", "Status": "Error", "Name": "TDX_IDE_STREAM_NOT_CONFIGURED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream is not configured" ] }, { "Status Code (Bits 63:32)": "0xC0000F1A", "Status": "Error", "Name": "TDX_IDE_STREAM_NOT_BLOCKED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream is not blocked" ] }, { "Status Code (Bits 63:32)": "0xC0000F1B", "Status": "Error", "Name": "TDX_IDE_STREAM_ADDR_OVERLAP", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream address range overlaps with another (configured IDE stream)" ] }, { "Status Code (Bits 63:32)": "0xC0000F1C", "Status": "Error", "Name": "TDX_IDE_STREAM_RID_OVERLAP", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream RID range overlaps with another (configured IDE stream)" ] }, { "Status Code (Bits 63:32)": "0xC0000F1F", "Status": "Error", "Name": "TDX_IDE_STREAM_HAS_DEVICE_INTERFACES", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream is associated with device interfaces" ] }, { "Status Code (Bits 63:32)": "0xC0000F21", "Status": "Error", "Name": "TDX_IDE_STREAM_IDEKM_KEYS_NOT_READY", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE key management protocol keys not ready" ] }, { "Status Code (Bits 63:32)": "0xC0000F23", "Status": "Error", "Name": "TDX_IDE_STREAM_IDEKM_INVALID_RESPONSE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE key managemnt invalid response" ] }, { "Status Code (Bits 63:32)": "0xC0000F24", "Status": "Error", "Name": "TDX_IDE_STREAM_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IDE stream invalid state" ] }, { "Status Code (Bits 63:32)": "0xC0000F25", "Status": "Error", "Name": "TDX_MMIO_INVALID_PAGE_METADATA", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Invalid MMIO page metadata" ] }, { "Status Code (Bits 63:32)": "0xC0000F26", "Status": "Error", "Name": "TDX_MMIO_ACCEPT_SIZE_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "MMIO accept page size mismatch" ] }, { "Status Code (Bits 63:32)": "0xC0000F27", "Status": "Error", "Name": "TDX_MMIO_TDI_OWNER_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "MMIO TDI onewer mismatch" ] }, { "Status Code (Bits 63:32)": "0xC0000F38", "Status": "Error", "Name": "TDX_DMAR_INDEX_OUT_OF_BOUNDS", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DMAR exceeds table bounds" ] }, { "Status Code (Bits 63:32)": "0xC0000F39", "Status": "Error", "Name": "TDX_DMAR_ENTRY_NOT_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "DMAR entry is not present" ] }, { "Status Code (Bits 63:32)": "0xC0000F3A", "Status": "Error", "Name": "TDX_TD_HAS_ATTACHED_DEVICES", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TD has arttached devices" ] }, { "Status Code (Bits 63:32)": "0xC0000F3B", "Status": "Error", "Name": "TDX_IOMMU_IOTLB_TRACKING_NOT_REQUIRED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IOTLB invalidation and tracking is not required" ] }, { "Status Code (Bits 63:32)": "0xC0000F3E", "Status": "Error", "Name": "TDX_IOMMU_KCB_MUST_BE_DISABLED", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "IOMMU configuration failed because KCB must be disabled" ] }, { "Status Code (Bits 63:32)": "0xC0000F3F", "Status": "Error", "Name": "TDX_TDI_HAS_MAPPED_DMA", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI can\u2019t be released because DMA is still mapped" ] }, { "Status Code (Bits 63:32)": "0xC0000F40", "Status": "Error", "Name": "TDX_TDIMT_NOT_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI metadata entry is not present" ] }, { "Status Code (Bits 63:32)": "0xC0000F41", "Status": "Error", "Name": "TDX_TDI_INVALID_METADATA", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Invalid TDI metadata entry" ] }, { "Status Code (Bits 63:32)": "0xC0000F42", "Status": "Error", "Name": "TDX_TDIMT_ALREADY_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI metadata entry is already present" ] }, { "Status Code (Bits 63:32)": "0xC0000F44", "Status": "Error", "Name": "TDX_SPDM_ENTRY_NOT_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "SPDM entry not found" ] }, { "Status Code (Bits 63:32)": "0xC0000F45", "Status": "Error", "Name": "TDX_SPDM_SESSION_KEY_REQUIRE_REFRESH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "SPDM session requires a key" ] }, { "Status Code (Bits 63:32)": "0xC0000F46", "Status": "Error", "Name": "TDX_CONNECT_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Invalid TDX Connect preserving state" ] }, { "Status Code (Bits 63:32)": "0xC0000F47", "Status": "Error", "Name": "TDX_MMIOMT_NOT_PRESENT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "MMIO metadata entry is not present" ] }, { "Status Code (Bits 63:32)": "0xC0000F48", "Status": "Error", "Name": "TDX_IOMMU_RP_INVALID_CONFIGURATION", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Invalid configuration in RP configuration registers" ] }, { "Status Code (Bits 63:32)": "0xC0000F49", "Status": "Error", "Name": "TDX_TDI_INVALID_TDI_CONFIGURATION", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "The device interface configuration is not supported by TDX Connect capabilities" ] }, { "Status Code (Bits 63:32)": "0xC0000F4B", "Status": "Error", "Name": "TDX_TDI_TDISP_INVALID_REPORT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI report is incomplete or invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000F4C", "Status": "Error", "Name": "TDX_MMIO_PAGE_NOT_IN_ASSOC_RANGE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "MMIO page is not in RP association range" ] }, { "Status Code (Bits 63:32)": "0xC0000F4D", "Status": "Error", "Name": "TDX_MMIO_INVALID_HPA_OFFSET", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "MMIO page address has invalid added offset " ] }, { "Status Code (Bits 63:32)": "0xC0000F4E", "Status": "Error", "Name": "TDX_SDPM_INVALID_MESSAGE", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "SPDM message is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0000F4F", "Status": "Error", "Name": "TDX_TPR_INVALID_STATE", "DETAILS_L2 (Bits 31:0)": [ "TPR index" ], "Description": [ "TPR ranges must be disabled" ] }, { "Status Code (Bits 63:32)": "0xC0000F50", "Status": "Error", "Name": "TDX_SMRR_OVERLAPS_IORANGE", "DETAILS_L2 (Bits 31:0)": [ "SMRR index" ], "Description": [ "SMRR overlaps I/O range" ] }, { "Status Code (Bits 63:32)": "0x80000F51", "Status": "Recover. Error", "Name": "TDX_IOMMU_ECMD_TIMEOUT", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Configure/Clear_IOMMU has not completed. Host must retry." ] }, { "Status Code (Bits 63:32)": "0x80000F52", "Status": "Recover. Error", "Name": "TDX_IOMMU_ECMD_ERROR", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "Configure/Clear_IOMMU failed. Host may retry." ] }, { "Status Code (Bits 63:32)": "0x00000F53", "Status": "Success", "Name": "TDX_GUEST_INV_NOT_REQUIRED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Guest invalidation is not required" ] }, { "Status Code (Bits 63:32)": "0xC0000F54", "Status": "Error", "Name": "TDX_GUEST_INV_IN_PROGRESS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Previous TD invalidation request is in progress" ] }, { "Status Code (Bits 63:32)": "0xC0000F55", "Status": "Error", "Name": "TDX_GUEST_INV_INVALID_DESC", "DETAILS_L2 (Bits 31:0)": [ "Entry index" ], "Description": [ "Invalid invalidation descriptor in TD request" ] }, { "Status Code (Bits 63:32)": "0x00000F56", "Status": "Success", "Name": "TDX_IOTLB_INV_REQUEST", "DETAILS_L2 (Bits 31:0)": [ "Number of descriptors to invalidate" ], "Description": [ "Request from the host VMM to invalidate IOTLB" ] }, { "Status Code (Bits 63:32)": "0xC0000F57", "Status": "Error", "Name": "TDX_SPDM_REQUEST", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "An SPDM request message was generated. The TDX Module is waiting for the corresponding SPDM response message in the next SEAMCALL invokation." ] }, { "Status Code (Bits 63:32)": "0xC0000F58", "Status": "Error", "Name": "TDX_NO_FREE_SPDM_SESSIONS", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "All SPDM sessions are in use." ] }, { "Status Code (Bits 63:32)": "0xC0000F59", "Status": "Error", "Name": "TDX_TDI_IRH_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "Operand ID" ], "Description": [ "TDI report hash mismatch" ] }, { "Status Code (Bits 63:32)": "0xC0000F5A", "Status": "Error", "Name": "TDX_TDISP_ERROR", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "An error was reported by the device in its TDISP response message." ] }, { "Status Code (Bits 63:32)": "0xC0000F5B", "Status": "Error", "Name": "TDX_NO_FREE_IDE_KEYS", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "All IDE stream key slots are in use." ] }, { "Status Code (Bits 63:32)": "0xC0000F5C", "Status": "Error", "Name": "TDX_TPR_RANGE_ENABLED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TPR Ranges must be disabled" ] }, { "Status Code (Bits 63:32)": "0xC0000F5D", "Status": "Error", "Name": "TDX_SPDM_NEEDS_ABORT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "SPDM session needs to be aborted to block the IDE stream with TDIs in RUN state" ] }, { "Status Code (Bits 63:32)": "0xC0000F5E", "Status": "Error", "Name": "TDX_SPDM_MESSAGE_ERROR", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "An SPDM error message was returned, the SPDM session establishment failed" ] }, { "Status Code (Bits 63:32)": "0xC0000F5F", "Status": "Error", "Name": "TDX_TDISP_MESSAGE_ERROR", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A TDISP error message was returned, the SPDM session establishment failed" ] }, { "Status Code (Bits 63:32)": "0xC0000F60", "Status": "Error", "Name": "TDX_TDI_TDISP_OUT_REQ", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A TDISP response message for a different TDISP operation is pending" ] }, { "Status Code (Bits 63:32)": "0xC0000F61", "Status": "Error", "Name": "TDX_MMIO_STILL_MAPPED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "All MMIO must be unmapped before PASIDTE DMAR block" ] }, { "Status Code (Bits 63:32)": "0xC0000F62", "Status": "Error", "Name": "RESERVED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "None" ] }, { "Status Code (Bits 63:32)": "0xC0000F63", "Status": "Error", "Name": "TDX_CONNECT_INCORRECT_TD_CONFIG", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TD configuration is incompatible with TDX Connect" ] }, { "Status Code (Bits 63:32)": "0x80000F64", "Status": "Recover. Error", "Name": "TDX_MAX_IDE_STREAMS_PER_SPDM_EXCEEDED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Max supported IDE Streams per SPDM session exceeded" ] }, { "Status Code (Bits 63:32)": "0xC0001000", "Status": "Error", "Name": "TDX_INVALID_CPUSVN", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "REPORTMACSTRUCT.CPUSVN is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0001001", "Status": "Error", "Name": "TDX_INVALID_REPORTMACSTRUCT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "REPORTMACSTRUCT is invalid" ] }, { "Status Code (Bits 63:32)": "0xC0001002", "Status": "Error", "Name": "TDX_TDG_MR_REPORT_VERSION_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDG.MR.REPORT was called with a version number that doesn't allow creating a report matching the TD's configuration" ] }, { "Status Code (Bits 63:32)": "0xC0001003", "Status": "Error", "Name": "TDX_INSUFFICIENT_TDREPORT_SPACE", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDG.MR.REPORT was provided with a buffer space that is too small for the generated TDREPORT_STRUCT" ] }, { "Status Code (Bits 63:32)": "0xC0001004", "Status": "Error", "Name": "TDX_MR_KEY_GET_NOT_SUPPORTED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDG.MR.KEY.GET is not supported for this TD (e.g., it is migratable)" ] }, { "Status Code (Bits 63:32)": "0xC0001005", "Status": "Error", "Name": "TDX_TDSIGSTRUCT_MISMATCH", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "One of the reference measurements in the TDSIGSTRUCT did not match the current measurements in the TDCS" ] }, { "Status Code (Bits 63:32)": "0xC0001006", "Status": "Error", "Name": "TDX_SVN_INVALID", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Requested SVN is invalid for current configuration" ] }, { "Status Code (Bits 63:32)": "0x00001100", "Status": "Success", "Name": "TDX_L2_EXIT_HOST_ROUTED_ASYNC", "DETAILS_L2 (Bits 31:0)": [ "For TDG.VP.ENTER: Exit Reason" ], "Description": [ "L1-to-L2 entry succeeded. Later, following an aynchronous TD exit from L2, the host VMM requested resumption of L1." ] }, { "Status Code (Bits 63:32)": "0x00001101", "Status": "Success", "Name": "TDX_L2_EXIT_HOST_ROUTED_TDVMCALL", "DETAILS_L2 (Bits 31:0)": [ "For TDG.VP.ENTER: Exit Reason" ], "Description": [ "L1-to-L2 entry succeeded. Later, following a TDG.VP.VMCALL TD exit from L2, the host VMM requested resumption of L1." ] }, { "Status Code (Bits 63:32)": "0x00001102", "Status": "Success", "Name": "TDX_L2_EXIT_PENDING_INTERRUPT", "DETAILS_L2 (Bits 31:0)": [ "For TDG.VP.ENTER: Exit Reason" ], "Description": [ "L1-to-L2 entry succeeded, and later L2-to-L1 exit happened due to an interrupt that was posted to L1 and is pending." ] }, { "Status Code (Bits 63:32)": "0x80001103", "Status": "Recover. Error", "Name": "TDX_L2_VM_ENTRY_FAILED", "DETAILS_L2 (Bits 31:0)": [ "For TDG.VP.ENTER: Exit Reason" ], "Description": [ "L2 VM entry failed due to incorrect setting of L2 VMCS." ] }, { "Status Code (Bits 63:32)": "0x00001120", "Status": "Success", "Name": "TDX_PENDING_INTERRUPT", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "L1-to-L2 entry was aborted because an interrupt is pending for the L1 VMM. This indication is returned even if the L1 VMMs cleared RFLAGS.IF." ] }, { "Status Code (Bits 63:32)": "0x00001140", "Status": "Success", "Name": "TDX_TD_EXIT_BEFORE_L2_ENTRY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "A debuggable TD's L1-to-L2 entry was mutated to a TD exit" ] }, { "Status Code (Bits 63:32)": "0x00001141", "Status": "Success", "Name": "TDX_TD_EXIT_ON_L2_VM_EXIT", "DETAILS_L2 (Bits 31:0)": [ "Exit Reason" ], "Description": [ "A debuggable TD's VM exit from L2 was mutated to a TD exit" ] }, { "Status Code (Bits 63:32)": "0x00001142", "Status": "Success", "Name": "TDX_TD_EXIT_ON_L2_TO_L1", "DETAILS_L2 (Bits 31:0)": [ "Exit Reason" ], "Description": [ "A debuggable TD's L2-to-L1 entry was mutated to a TD exit" ] }, { "Status Code (Bits 63:32)": "0xC0001160", "Status": "Error", "Name": "TDX_GLA_NOT_CANONICAL", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "Guest linear address is not canonical" ] }, { "Status Code (Bits 63:32)": "0xC0001200", "Status": "Error", "Name": "TDX_EXT_FATAL_ERROR", "DETAILS_L2 (Bits 31:0)": [ "Bits 15:0: Extension Error Code", "Bits 31:16: Extension Type" ], "Description": [ "NRX Fatal error, TDX module reinstall is required" ] }, { "Status Code (Bits 63:32)": "0x80001201", "Status": "Recover. Error", "Name": "TDX_EXT_MEMORY_POOL_NOT_READY", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDH.EXT.INIT was called before the memory pool is ready" ] }, { "Status Code (Bits 63:32)": "0x80001202", "Status": "Recover. Error", "Name": "TDX_EXT_MEMORY_POOL_NOT_PENDING", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDH.EXT.MEM.ADD was called but extention state is not memory pending" ] }, { "Status Code (Bits 63:32)": "0x00001203", "Status": "Success", "Name": "TDX_EXT_MEMORY_POOL_FULL", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "The NRX memory pool is full" ] }, { "Status Code (Bits 63:32)": "0x80001204", "Status": "Recover. Error", "Name": "TDX_EXT_NOT_INITIALIZED", "DETAILS_L2 (Bits 31:0)": [ "0" ], "Description": [ "TDX Extension was not initialized" ] }, { "Status Code (Bits 63:32)": "0x80001205", "Status": "Recover. Error", "Name": "TDX_EXT_NOT_READY", "DETAILS_L2 (Bits 31:0)": [ "Extension ID" ], "Description": [ "TDX Extension not ready" ] } ] }