{
  "Header": {
    "Copyright": "Copyright (c) 2022 - 2023 Intel Corporation. All rights reserved.",
    "Info": "TDX MSR Preservation after TD Enty/Exit Summary",
    "Version": "2.0"
  },
  "Description": [
    {
      "Text": "INIT",
      "State Preservation": "The TDX Module sets the MSR to its RESET value."
    },
    {
      "Text": "Init(condition)",
      "State Preservation": "If the condition is true, the TDX Module sets the MSR to its RESET value.  Else the MSR value is unmodified."
    },
    {
      "Text": "Modified(condition)",
      "State Preservation": "If the condition is true, the MSR value may be modified.  Else the MSR value is unmodified."
    }
  ],
  "MSRs": [
    {
      "MSR Index Range": {
        "First": "0x00C1",
        "Last": "0x00C8",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_PMCx",
      "MSR Value after TDH.VP.ENTER": [
        "Implicit (via IA32_A_PMCx):",
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00E1",
        "Last": "0x00E1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UMWAIT_CONTROL",
      "MSR Value after TDH.VP.ENTER": [
        "Init(virt. CPUID(7,0).ECX[5])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0122",
        "Last": "0x0122",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSX_CTRL",
      "MSR Value after TDH.VP.ENTER": [
        "Init(virt. TSX enabled)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0186",
        "Last": "0x018D",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_PERFEVTSELx",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01A6",
        "Last": "0x01A7",
        "Size": "0x2"
      },
      "MSR Architectural Name": "MSR_OFFCORE_RSPx",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C4",
        "Last": "0x01C4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XFD",
      "MSR Value after TDH.VP.ENTER": [
        "Init(virt. CPUID(0xD,0x1).EAX[4])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C5",
        "Last": "0x01C5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XFD_ERR",
      "MSR Value after TDH.VP.ENTER": [
        "Init(virt. CPUID(0xD,0x1).EAX[4])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D9",
        "Last": "0x01D9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DEBUGCTL",
      "MSR Value after TDH.VP.ENTER": [
        "INIT, except for the following bits which are preserved:",
        "Bit 1 (BTF)",
        "Bit 12 (FREEZE_PERFMON_ON_PMI)",
        "Bit 14 (FREEZE_WHILE_SMM)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0309",
        "Last": "0x0310",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_FIXED_CTRx",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0329",
        "Last": "0x0329",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_METRICS",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON && IA32_PERF_CAPABILITIES[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038D",
        "Last": "0x038D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FIXED_CTR_CTRL",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038E",
        "Last": "0x038E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_STATUS",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038F",
        "Last": "0x038F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_CTRL",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F1",
        "Last": "0x03F1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PEBS_ENABLE",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F2",
        "Last": "0x03F2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_MATRIX_VECT",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F6",
        "Last": "0x03F6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_LD_LATENCY",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F7",
        "Last": "0x03F7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_FRONTEND",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x04C1",
        "Last": "0x04C8",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_A_PMCx",
      "MSR Value after TDH.VP.ENTER": [
        "Init(PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0560",
        "Last": "0x0560",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_OUTPUT_BASE",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0561",
        "Last": "0x0561",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_OUTPUT_MASK_PTRS",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0570",
        "Last": "0x0570",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_CTL",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0571",
        "Last": "0x0571",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_STATUS",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0572",
        "Last": "0x0572",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_CR3_MATCH",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0580",
        "Last": "0x0580",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR0_A",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0581",
        "Last": "0x0581",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR0_B",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0582",
        "Last": "0x0582",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR1_A",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0583",
        "Last": "0x0583",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR1_B",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0584",
        "Last": "0x0584",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR2_A",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0585",
        "Last": "0x0585",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR2_B",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0586",
        "Last": "0x0586",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR3_A",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0587",
        "Last": "0x0587",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR3_B",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM(8))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A0",
        "Last": "0x06A0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_U_CET",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A4",
        "Last": "0x06A4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL0_SSP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A5",
        "Last": "0x06A5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL1_SSP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A6",
        "Last": "0x06A6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL2_SSP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A7",
        "Last": "0x06A7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL3_SSP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0985",
        "Last": "0x0985",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_RR",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0986",
        "Last": "0x0986",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_HANDLER",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0987",
        "Last": "0x0987",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_STACKADJUST",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0988",
        "Last": "0x0988",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_MISC",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0989",
        "Last": "0x0989",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_PD",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098A",
        "Last": "0x098A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_TT",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DA0",
        "Last": "0x0DA0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XSS",
      "MSR Value after TDH.VP.ENTER": [
        "Supervisor-mode feature bits of XFAM (bits 8, 16:10)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1200",
        "Last": "0x12FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_INFO",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x14CE",
        "Last": "0x14CE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LBR_CTL",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x14CF",
        "Last": "0x14CF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LBR_DEPTH",
      "MSR Value after TDH.VP.ENTER": [
        "Modified(XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1500",
        "Last": "0x15FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_x_FROM_IP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1600",
        "Last": "0x16FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_x_TO_IP",
      "MSR Value after TDH.VP.ENTER": [
        "Init(XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1B01",
        "Last": "0x1B01",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UARCH_MISC_CTL",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000081",
        "Last": "0xC0000081",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_STAR",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000082",
        "Last": "0xC0000082",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LSTAR",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000084",
        "Last": "0xC0000084",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FMASK",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000102",
        "Last": "0xC0000102",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_KERNEL_GS_BASE",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000103",
        "Last": "0xC0000103",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSC_AUX",
      "MSR Value after TDH.VP.ENTER": [
        "INIT"
      ]
    }
  ]
}