{
  "Header": {
    "Copyright": "Copyright (c) 2022 - 2023 Intel Corporation. All rights reserved.",
    "Info": "TDX MSR Virtualization",
    "Version": "2.0"
  },
  "Description": [
    {
      "Text": "Native",
      "Virtualization": [
        "Direct read or write from/to CPU"
      ]
    },
    {
      "Text": "#GP(0)",
      "Virtualization": [
        "Inject a #GP(0) exception"
      ]
    },
    {
      "Text": "#VE",
      "Virtualization": [
        "For L1:  Inject a #VE(NON_CONFIG_PARAVIRT) exception",
        "For L2:  L2->L1"
      ]
    },
    {
      "Text": "Inject_GP(condition)",
      "Virtualization": [
        "TDX Module injects a #GP(0) if condition is true, else reads from CPU or write to CPU:",
        "    if (condition)",
        "        #GP(0)",
        "    else",
        "        Native"
      ]
    },
    {
      "Text": "Inject_GP_or_VE(condition)",
      "Virtualization": [
        "TDX Module injects a #GP(0) if condition is true, else it injects a #VE or does an L2->L1 exit as described above:",
        "    if (condition)",
        "        #GP(0)",
        "    else",
        "       if L1, #VE(CONFIG_PARAVIRT)",
        "       if L2, L2->L1 exit"
      ]
    }
  ],
  "MSRs": [
    {
      "MSR Index Range": {
        "First": "Default",
        "Last": "Default",
        "Size": "N/A"
      },
      "MSR Architectural Name": "Any MSR not in this table whose index is in 0x0-0x1FFF nor 0xC0000000-0xC0001FFF",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0010",
        "Last": "0x0010",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TIME_STAMP_COUNTER",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "#VE"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0017",
        "Last": "0x0017",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PLATFORM_ID",
      "On RDMSR": [
        "#VE"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x001C",
        "Last": "0x001C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x002F",
        "Last": "0x002F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0033",
        "Last": "0x0033",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_MEMORY_CTRL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0034",
        "Last": "0x0034",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_SMI_COUNT",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    read from TDVPS",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    write to TDVPS",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x003A",
        "Last": "0x003A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FEATURE_CONTROL",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    return 1 (locked)",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x003B",
        "Last": "0x003B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSC_ADJUST",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0048",
        "Last": "0x0048",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SPEC_CTRL",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0049",
        "Last": "0x0049",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PRED_CMD",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x004E",
        "Last": "0x004E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PPIN_CTL",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    return 1 (locked, disabled)",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x004F",
        "Last": "0x004F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PPIN",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0079",
        "Last": "0x0079",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_BIOS_UPDT_TRIG",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    ignore",
        "else",
        "    #VE(CONFIG_PARAVIRT"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x007A",
        "Last": "0x007A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FEATURE_ACTIVATION",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0082",
        "Last": "0x0082",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FZM_RANGE_INDEX",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0083",
        "Last": "0x0083",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FZM_DOMAIN_CONFIG",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0084",
        "Last": "0x0084",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FZM_RANGE_STARTADDR",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0085",
        "Last": "0x0085",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FZM_RANGE_ENDADDR",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0086",
        "Last": "0x0086",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FZM_RANGE_WRITESTATUS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0087",
        "Last": "0x0087",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MKTME_PARTITIONING",
      "On RDMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).EDX[18])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).EDX[18])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x008B",
        "Last": "0x008B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_BIOS_SIGN_ID",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    return 0xFFFFFFFF",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    ignore",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x008C",
        "Last": "0x008F",
        "Size": "0x4"
      },
      "MSR Architectural Name": "IA32_SGXLEPUBKEYHASHx",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0098",
        "Last": "0x0098",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_WBINVDP",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0099",
        "Last": "0x0099",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_WBNOINVDP",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x009A",
        "Last": "0x009A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_INTR_PENDING",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x009B",
        "Last": "0x009B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMM_MONITOR_CTL",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x009E",
        "Last": "0x009E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMBASE",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00BC",
        "Last": "0x00BC",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MISC_PACKAGE_CTLS",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "#VE"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00BD",
        "Last": "0x00BD",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XAPIC_DISABLE_STATUS",
      "On RDMSR": [
        "Bit 0 (LEGACY_APIC_DISABLED) = 1",
        "Other bits are 0"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00C1",
        "Last": "0x00C8",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_PMCx",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00CE",
        "Last": "0x00CE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PLATFORM_INFO",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    return 0",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00CF",
        "Last": "0x00CF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_CORE_CAPABILITIES",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00E1",
        "Last": "0x00E1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UMWAIT_CONTROL",
      "On RDMSR": [
        "Inject_GP(~virt. CPUID(7,0).ECX[5])"
      ],
      "On WRMSR": [
        "Inject_GP(~virt. CPUID(7,0).ECX[5])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00E7",
        "Last": "0x00E7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPERF",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00E8",
        "Last": "0x00E8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_APERF",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00ED",
        "Last": "0x00ED",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_RAR_CONTROL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00EE",
        "Last": "0x00EE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_RAR_ACTION_VECTOR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00EF",
        "Last": "0x00EF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_RAR_PAYLOAD_TABLE_BASE ",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00F0",
        "Last": "0x00F0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_RAR_INFO",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EDX[30])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x00FE",
        "Last": "0x00FE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRRCAP",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x010A",
        "Last": "0x010A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_ARCH_CAPABILITIES",
      "On RDMSR": [
        "See the [Base Spec] section on IA32_ARCH_CAPABILITIES MSR"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x010B",
        "Last": "0x010B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FLUSH_CMD",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x010F",
        "Last": "0x010F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSX_FORCE_ABORT",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0122",
        "Last": "0x0122",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSX_CTRL",
      "On RDMSR": [
        "Inject_GP(~(virt. TSX enabled))"
      ],
      "On WRMSR": [
        "Inject_GP(~(virt. TSX enabled))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0123",
        "Last": "0x0123",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MCU_OPT_CTRL",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0140",
        "Last": "0x0140",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_FEATURE_ENABLES",
      "On RDMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    return 0",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    if value == 0, ignore",
        "    else #GP",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0174",
        "Last": "0x0174",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SYSENTER_CS",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0175",
        "Last": "0x0175",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SYSENTER_ESP",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0176",
        "Last": "0x0176",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SYSENTER_EIP",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0179",
        "Last": "0x0179",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MCG_CAP",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x017A",
        "Last": "0x017A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MCG_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x017B",
        "Last": "0x017B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MCG_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0186",
        "Last": "0x018D",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_PERFEVTSELx",
      "On RDMSR": [
        "if (EVENT_FILTERS_NUM > 0)",
        "    Special event filtering",
        "else ",
        "    #GP(0)"
      ],
      "On WRMSR": [
        "if (!PERFMON)",
        "    #GP(0)",
        "if (EVENT_FILTERS_NUM > 0)",
        "    Special event filtering"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0195",
        "Last": "0x0195",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_OVERCLOCKING_STATUS",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0198",
        "Last": "0x0198",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[7])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[7])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0199",
        "Last": "0x0199",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[7])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[7])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x019A",
        "Last": "0x019A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_CLOCK_MODULATION",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x019B",
        "Last": "0x019B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_THERM_INTERRUPT",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x019C",
        "Last": "0x019C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_THERM_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[22])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x019D",
        "Last": "0x019D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_THERM2_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[8])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).ECX[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x019E",
        "Last": "0x019E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01A0",
        "Last": "0x01A0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MISC_ENABLE",
      "On RDMSR": [
        "Read from TDVPS"
      ],
      "On WRMSR": [
        "if TD_CTLS.REDUCE_VE",
        "    write to TDVPS, see [ABI",
        "    Spec] for details",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01A6",
        "Last": "0x01A7",
        "Size": "0x2"
      },
      "MSR Architectural Name": "MSR_OFFCORE_RSPx",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01B0",
        "Last": "0x01B0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_ENERGY_PERF_BIAS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01B1",
        "Last": "0x01B1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PACKAGE_THERM_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01B2",
        "Last": "0x01B2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PACKAGE_THERM_INTERRUPT",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C2",
        "Last": "0x01C2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HW_GET_LP_PM_META_DATA",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C3",
        "Last": "0x01C3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HW_SET_LP_PM_META_DATA",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C4",
        "Last": "0x01C4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XFD",
      "On RDMSR": [
        "Inject_GP(~(virt. CPUID(0xD,0x1).EAX[4]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(virt. CPUID(0xD,0x1).EAX[4]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C5",
        "Last": "0x01C5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XFD_ERR",
      "On RDMSR": [
        "Inject_GP(~(virt. CPUID(0xD,0x1).EAX[4]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(virt. CPUID(0xD,0x1).EAX[4]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01C7",
        "Last": "0x01C7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DD_TRHTTLE_DEACTIVATE_MSR ",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CA",
        "Last": "0x01CA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DD_DI_CAPABILITY_MSR ",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CB",
        "Last": "0x01CB",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DD_DI_ACTIVATE_MSR ",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CC",
        "Last": "0x01CC",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CD",
        "Last": "0x01CD",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CE",
        "Last": "0x01CE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01CF",
        "Last": "0x01CF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D0",
        "Last": "0x01D0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D1",
        "Last": "0x01D1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D2",
        "Last": "0x01D2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D3",
        "Last": "0x01D3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D4",
        "Last": "0x01D4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01D9",
        "Last": "0x01D9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DEBUGCTL",
      "On RDMSR": [
        "Clear ENABLE_UNCORE_PMI (bit 13)"
      ],
      "On WRMSR": [
        "#GP if invalid, #VE if value is not supported for TD.",
        "For details see the [Base Spec] Debug and Profiling Architecture chapter."
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F2",
        "Last": "0x01F2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMRR_PHYSBASE",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F3",
        "Last": "0x01F3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMRR_PHYSMASK",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F6",
        "Last": "0x01F6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMRR2_PHYSBASE",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F7",
        "Last": "0x01F7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SMRR2_PHYSMASK",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F8",
        "Last": "0x01F8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PLATFORM_DCA_CAP",
      "On RDMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01F9",
        "Last": "0x01F9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_CPU_DCA_CAP",
      "On RDMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x01FA",
        "Last": "0x01FA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DCA_0_CAP",
      "On RDMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE( ~virt. CPUID(0x1).ECX[18])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0200",
        "Last": "0x0200",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE0",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0201",
        "Last": "0x0201",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK0",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0202",
        "Last": "0x0202",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE1",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0203",
        "Last": "0x0203",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK1",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0204",
        "Last": "0x0204",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE2",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0205",
        "Last": "0x0205",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK2",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0206",
        "Last": "0x0206",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE3",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0207",
        "Last": "0x0207",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK3",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0208",
        "Last": "0x0208",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE4",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0209",
        "Last": "0x0209",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK4",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020A",
        "Last": "0x020A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE5",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020B",
        "Last": "0x020B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK5",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020C",
        "Last": "0x020C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE6",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020D",
        "Last": "0x020D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK6",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020E",
        "Last": "0x020E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE7",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x020F",
        "Last": "0x020F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK7",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0210",
        "Last": "0x0210",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE8",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0211",
        "Last": "0x0211",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK8",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0212",
        "Last": "0x0212",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSBASE9",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0213",
        "Last": "0x0213",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_PHYSMASK9",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0250",
        "Last": "0x0250",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX64K_00000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0258",
        "Last": "0x0258",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX16K_80000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0259",
        "Last": "0x0259",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX16K_A0000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0268",
        "Last": "0x0268",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_C0000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0269",
        "Last": "0x0269",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_C8000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026A",
        "Last": "0x026A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_D0000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026B",
        "Last": "0x026B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_D8000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026C",
        "Last": "0x026C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_E0000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026D",
        "Last": "0x026D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_E8000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026E",
        "Last": "0x026E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_F0000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x026F",
        "Last": "0x026F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_FIX4K_F8000",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0276",
        "Last": "0x0276",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_SLAM_ENABLE",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0277",
        "Last": "0x0277",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PAT",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0280",
        "Last": "0x029F",
        "Size": "0x20"
      },
      "MSR Architectural Name": "IA32_MCx_CTL2",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x02A0",
        "Last": "0x02A7",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_PRMRR_BASEx",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x02C0",
        "Last": "0x02C0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FUSARR_BASE",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x02C1",
        "Last": "0x02C1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FUSARR_MASK",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x02FF",
        "Last": "0x02FF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MTRR_DEF_TYPE",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0302",
        "Last": "0x0302",
        "Size": "0x1"
      },
      "MSR Architectural Name": "BIOS_SE_SVN",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0303",
        "Last": "0x0303",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Future BIOS_SE_SVN Expansion",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0309",
        "Last": "0x0310",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_FIXED_CTRx",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0329",
        "Last": "0x0329",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_METRICS",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0345",
        "Last": "0x0345",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_CAPABILITIES",
      "On RDMSR": [
        "if ~PERFMON",
        "    return 0",
        "else if ~XFAM[8]",
        "    clear bit 16",
        "else",
        "    Native"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038D",
        "Last": "0x038D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FIXED_CTR_CTRL",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038E",
        "Last": "0x038E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_STATUS",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x038F",
        "Last": "0x038F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_CTRL",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0390",
        "Last": "0x0390",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_STATUS_RESET",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0391",
        "Last": "0x0391",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_STATUS_SET",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0392",
        "Last": "0x0392",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PERF_GLOBAL_INUSE",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F1",
        "Last": "0x03F1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PEBS_ENABLE",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F2",
        "Last": "0x03F2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_MATRIX_VECT",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F3",
        "Last": "0x03F3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F4",
        "Last": "0x03F4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F5",
        "Last": "0x03F5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F6",
        "Last": "0x03F6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_LD_LATENCY",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x03F7",
        "Last": "0x03F7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "MSR_PEBS_FRONTEND",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0400",
        "Last": "0x0400",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC0_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0401",
        "Last": "0x0401",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC0_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0402",
        "Last": "0x0402",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC0_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0403",
        "Last": "0x0403",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC0_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0404",
        "Last": "0x0404",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC1_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0405",
        "Last": "0x0405",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC1_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0406",
        "Last": "0x0406",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC1_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0407",
        "Last": "0x0407",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC1_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0408",
        "Last": "0x0408",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC2_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0409",
        "Last": "0x0409",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC2_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040A",
        "Last": "0x040A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC2_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040B",
        "Last": "0x040B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC2_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040C",
        "Last": "0x040C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC3_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040D",
        "Last": "0x040D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC3_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040E",
        "Last": "0x040E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC3_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x040F",
        "Last": "0x040F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC3_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0410",
        "Last": "0x0410",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC4_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0411",
        "Last": "0x0411",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC4_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0412",
        "Last": "0x0412",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC4_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0413",
        "Last": "0x0413",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC4_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0414",
        "Last": "0x0414",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC5_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0415",
        "Last": "0x0415",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC5_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0416",
        "Last": "0x0416",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC5_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0417",
        "Last": "0x0417",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC5_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0418",
        "Last": "0x0418",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC6_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0419",
        "Last": "0x0419",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC6_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041A",
        "Last": "0x041A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC6_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041B",
        "Last": "0x041B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC6_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041C",
        "Last": "0x041C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC7_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041D",
        "Last": "0x041D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC7_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041E",
        "Last": "0x041E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC7_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x041F",
        "Last": "0x041F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC7_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0420",
        "Last": "0x0420",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC8_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0421",
        "Last": "0x0421",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC8_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0422",
        "Last": "0x0422",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC8_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0423",
        "Last": "0x0423",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC8_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0424",
        "Last": "0x0424",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC9_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0425",
        "Last": "0x0425",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC9_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0426",
        "Last": "0x0426",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC9_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0427",
        "Last": "0x0427",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC9_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0428",
        "Last": "0x0428",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC10_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0429",
        "Last": "0x0429",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC10_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042A",
        "Last": "0x042A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC10_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042B",
        "Last": "0x042B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC10_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042C",
        "Last": "0x042C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC11_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042D",
        "Last": "0x042D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC11_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042E",
        "Last": "0x042E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC11_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x042F",
        "Last": "0x042F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC11_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0430",
        "Last": "0x0430",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC12_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0431",
        "Last": "0x0431",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC12_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0432",
        "Last": "0x0432",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC12_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0433",
        "Last": "0x0433",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC12_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0434",
        "Last": "0x0434",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC13_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0435",
        "Last": "0x0435",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC13_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0436",
        "Last": "0x0436",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC13_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0437",
        "Last": "0x0437",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC13_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0438",
        "Last": "0x0438",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC14_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0439",
        "Last": "0x0439",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC14_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043A",
        "Last": "0x043A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC14_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043B",
        "Last": "0x043B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC14_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043C",
        "Last": "0x043C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC15_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043D",
        "Last": "0x043D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC15_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043E",
        "Last": "0x043E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC15_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x043F",
        "Last": "0x043F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC15_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0440",
        "Last": "0x0440",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC16_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0441",
        "Last": "0x0441",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC16_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0442",
        "Last": "0x0442",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC16_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0443",
        "Last": "0x0443",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC16_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0444",
        "Last": "0x0444",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC17_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0445",
        "Last": "0x0445",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC17_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0446",
        "Last": "0x0446",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC17_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0447",
        "Last": "0x0447",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC17_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0448",
        "Last": "0x0448",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC18_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0449",
        "Last": "0x0449",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC18_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044A",
        "Last": "0x044A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC18_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044B",
        "Last": "0x044B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC18_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044C",
        "Last": "0x044C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC19_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044D",
        "Last": "0x044D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC19_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044E",
        "Last": "0x044E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC19_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x044F",
        "Last": "0x044F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC19_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0450",
        "Last": "0x0450",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC20_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0451",
        "Last": "0x0451",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC20_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0452",
        "Last": "0x0452",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC20_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0453",
        "Last": "0x0453",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC20_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0454",
        "Last": "0x0454",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC21_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0455",
        "Last": "0x0455",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC21_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0456",
        "Last": "0x0456",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC21_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0457",
        "Last": "0x0457",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC21_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0458",
        "Last": "0x0458",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC22_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0459",
        "Last": "0x0459",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC22_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045A",
        "Last": "0x045A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC22_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045B",
        "Last": "0x045B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC22_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045C",
        "Last": "0x045C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC23_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045D",
        "Last": "0x045D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC23_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045E",
        "Last": "0x045E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC23_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x045F",
        "Last": "0x045F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC23_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0460",
        "Last": "0x0460",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC24_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0461",
        "Last": "0x0461",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC24_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0462",
        "Last": "0x0462",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC24_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0463",
        "Last": "0x0463",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC24_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0464",
        "Last": "0x0464",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC25_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0465",
        "Last": "0x0465",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC25_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0466",
        "Last": "0x0466",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC25_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0467",
        "Last": "0x0467",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC25_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0468",
        "Last": "0x0468",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC26_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0469",
        "Last": "0x0469",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC26_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046A",
        "Last": "0x046A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC26_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046B",
        "Last": "0x046B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC26_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046C",
        "Last": "0x046C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC27_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046D",
        "Last": "0x046D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC27_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046E",
        "Last": "0x046E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC27_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x046F",
        "Last": "0x046F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC27_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0470",
        "Last": "0x0470",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC28_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0471",
        "Last": "0x0471",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC28_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0472",
        "Last": "0x0472",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC28_ADDR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0473",
        "Last": "0x0473",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MC28_MISC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0480",
        "Last": "0x0480",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_BASIC",
      "On RDMSR": [
        "For L1:",
        "Bit 54 (VM exit info on INS/OUTS) = 1",
        "Bit 55(true VMX controls) = 1",
        "Bit 56 (VOE w/o err code) = 1",
        "Bit 58 (Nested Exc.) = 0",
        "Other bits = 0",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0481",
        "Last": "0x0481",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_PINBASED_CTLS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0482",
        "Last": "0x0482",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_PROCBASED_CTLS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0483",
        "Last": "0x0483",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_EXIT_CTLS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0484",
        "Last": "0x0484",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_ENTRY_CTLS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0485",
        "Last": "0x0485",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_MISC",
      "On RDMSR": [
        "For L1:",
        "Bit 5 (unrestricted guest) = 1",
        "Bit 6 (HLT activity state) = 1",
        "Bit 7 (shutdown activity state) = 1",
        "Bit 14 (PT in VMX) = 1",
        "Bits 24:16 (CR3 target count) = 4",
        "Bit 29 (VMWRITE any field) = 1",
        "Bit 30 (VOE with 0 inst length) = 1",
        "Other bits = 0",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0486",
        "Last": "0x0486",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_CR0_FIXED0",
      "On RDMSR": [
        "For L1:  See L2 VMCS guest CR0 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0487",
        "Last": "0x0487",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_CR0_FIXED1",
      "On RDMSR": [
        "For L1:  See L2 VMCS guest CR0 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0488",
        "Last": "0x0488",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_CR4_FIXED0",
      "On RDMSR": [
        "For L1:  See L2 VMCS guest CR4 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0489",
        "Last": "0x0489",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_CR4_FIXED1",
      "On RDMSR": [
        "For L1:  See L2 VMCS guest CR4 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048A",
        "Last": "0x048A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_VMCS_ENUM",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048B",
        "Last": "0x048B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_PROCBASED_CTLS2",
      "On RDMSR": [
        "For L1:  See L2 VMCS controls 2 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048C",
        "Last": "0x048C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_EPT_VPID_CAP",
      "On RDMSR": [
        "For L1:",
        "Execute-only (bit 0) = 1",
        "2MB pages (bit 16) = 1",
        "1GB pages (bit 17) = 1",
        "A/D (bit 21) = 0",
        "EPT violation info (bit 22) = 1",
        "SSS (bit 23) = XFAM.CET_S (bit 12)",
        "HLAT prefix size (bits 53:48) taken from real MSR",
        "Other bits = 0",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048D",
        "Last": "0x048D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_TRUE_PINBASED_CTLS",
      "On RDMSR": [
        "For L1:  See L2 VMCS pinbased controls  field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048E",
        "Last": "0x048E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_TRUE_PROCBASED_CTLS",
      "On RDMSR": [
        "For L1:  See L2 VMCS procbased controls field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x048F",
        "Last": "0x048F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_TRUE_EXIT_CTLS",
      "On RDMSR": [
        "For L1:  See L2 VMCS VM exit controls field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0490",
        "Last": "0x0490",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_TRUE_ENTRY_CTLS",
      "On RDMSR": [
        "For L1:  See L2 VMCS VM entry controls field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0491",
        "Last": "0x0491",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_VMFUNC",
      "On RDMSR": [
        "For L1:  All-0",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0492",
        "Last": "0x0492",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_VMX_PROCBASED_CTLS3",
      "On RDMSR": [
        "For L1:  See L2 VMCS procbased controls3 field description",
        "For L2:  inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0493",
        "Last": "0x0493",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x04C0",
        "Last": "0x04C0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x04C1",
        "Last": "0x04C8",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_A_PMCx",
      "On RDMSR": [
        "Inject_GP(~PERFMON)"
      ],
      "On WRMSR": [
        "Inject_GP(~PERFMON)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x04D0",
        "Last": "0x04D0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MCG_EXT_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(1).EDX[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0500",
        "Last": "0x0500",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SGX_SVN_STATUS",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0501",
        "Last": "0x0501",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Future IA32_SE_SVN Expansion",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0550",
        "Last": "0x0550",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0551",
        "Last": "0x0551",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0560",
        "Last": "0x0560",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_OUTPUT_BASE",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0561",
        "Last": "0x0561",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_OUTPUT_MASK_PTRS",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0570",
        "Last": "0x0570",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_CTL",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0571",
        "Last": "0x0571",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_STATUS",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0572",
        "Last": "0x0572",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_CR3_MATCH",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0580",
        "Last": "0x0580",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR0_A",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0581",
        "Last": "0x0581",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR0_B",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0582",
        "Last": "0x0582",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR1_A",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0583",
        "Last": "0x0583",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR1_B",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0584",
        "Last": "0x0584",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR2_A",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0585",
        "Last": "0x0585",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR2_B",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0586",
        "Last": "0x0586",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR3_A",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0587",
        "Last": "0x0587",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_RTIT_ADDR3_B",
      "On RDMSR": [
        "Inject_GP(~XFAM[8])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[8])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D0",
        "Last": "0x05D0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_CAP",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D1",
        "Last": "0x05D1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_DEFAULT",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D2",
        "Last": "0x05D2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR1",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D3",
        "Last": "0x05D3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR1",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D4",
        "Last": "0x05D4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR1",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D5",
        "Last": "0x05D5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR2",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D6",
        "Last": "0x05D6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR2",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D7",
        "Last": "0x05D7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR2",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D8",
        "Last": "0x05D8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR3",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05D9",
        "Last": "0x05D9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR3",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DA",
        "Last": "0x05DA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR3",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DB",
        "Last": "0x05DB",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR4",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DC",
        "Last": "0x05DC",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR4",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DD",
        "Last": "0x05DD",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR4",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DE",
        "Last": "0x05DE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR5",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05DF",
        "Last": "0x05DF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR5",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E0",
        "Last": "0x05E0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR5",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E1",
        "Last": "0x05E1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR6",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E2",
        "Last": "0x05E2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR6",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E3",
        "Last": "0x05E3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR6",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E4",
        "Last": "0x05E4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR7",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E5",
        "Last": "0x05E5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR7",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E6",
        "Last": "0x05E6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR7",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E7",
        "Last": "0x05E7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR8",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E8",
        "Last": "0x05E8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR8",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05E9",
        "Last": "0x05E9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR8",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05EA",
        "Last": "0x05EA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR9",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05EB",
        "Last": "0x05EB",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR9",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05EC",
        "Last": "0x05EC",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR9",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05ED",
        "Last": "0x05ED",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR10",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05EE",
        "Last": "0x05EE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR10",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05EF",
        "Last": "0x05EF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR10",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F0",
        "Last": "0x05F0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR11",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F1",
        "Last": "0x05F1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR11",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F2",
        "Last": "0x05F2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR11",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F3",
        "Last": "0x05F3",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR12",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F4",
        "Last": "0x05F4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR12",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F5",
        "Last": "0x05F5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR12",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F6",
        "Last": "0x05F6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR13",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F7",
        "Last": "0x05F7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR13",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F8",
        "Last": "0x05F8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR13",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05F9",
        "Last": "0x05F9",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR14",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05FA",
        "Last": "0x05FA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR14",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05FB",
        "Last": "0x05FB",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR_ATTR14",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05FC",
        "Last": "0x05FC",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_LOW_ADDR15",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x05FD",
        "Last": "0x05FD",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_HIGH_ADDR15",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0600",
        "Last": "0x0600",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DS_AREA",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A0",
        "Last": "0x06A0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_U_CET",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A2",
        "Last": "0x06A2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_S_CET",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A4",
        "Last": "0x06A4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL0_SSP",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12])"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A5",
        "Last": "0x06A5",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL1_SSP",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A6",
        "Last": "0x06A6",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL2_SSP",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A7",
        "Last": "0x06A7",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PL3_SSP",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06A8",
        "Last": "0x06A8",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_INTERRUPT_SSP_TABLE_ADDR",
      "On RDMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ],
      "On WRMSR": [
        "Inject_GP(~(XFAM[11] | XFAM[12]))"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06E0",
        "Last": "0x06E0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSC_DEADLINE",
      "On RDMSR": [
        "inject_GP_or_VE( ~virt. CPUID(0x1).ECX[24])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE( ~virt. CPUID(0x1).ECX[24])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x06E1",
        "Last": "0x06E1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PKRS",
      "On RDMSR": [
        "Inject_GP(~PKS)"
      ],
      "On WRMSR": [
        "Inject_GP(~PKS)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0770",
        "Last": "0x0770",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PM_ENABLE",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0771",
        "Last": "0x0771",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_CAPABILITIES",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0772",
        "Last": "0x0772",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_REQUEST_PKG",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0773",
        "Last": "0x0773",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_INTERRUPT",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0774",
        "Last": "0x0774",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_REQUEST",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0775",
        "Last": "0x0775",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_PECI_REQUEST_INFO",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0776",
        "Last": "0x0776",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0777",
        "Last": "0x0777",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HWP_STATUS",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0793",
        "Last": "0x0793",
        "Size": "0x1"
      },
      "MSR Architectural Name": "EXTENDED_MCG_PTR",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0800",
        "Last": "0x0801",
        "Size": "0x2"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0802",
        "Last": "0x0802",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_APICID",
      "On RDMSR": [
        "if TD_CTLS.ENUM_TOPOLOGY",
        "    return virtual x2APIC ID",
        "else",
        "    #VE(CONFIG_PARAVIRT)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0803",
        "Last": "0x0803",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_VERSION",
      "On RDMSR": [
        "#VE"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0804",
        "Last": "0x0807",
        "Size": "0x4"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0808",
        "Last": "0x0808",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_TPR",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0809",
        "Last": "0x0809",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x080A",
        "Last": "0x080A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_PPR",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x080B",
        "Last": "0x080B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_EOI",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x080C",
        "Last": "0x080C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x080D",
        "Last": "0x080D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_LDR",
      "On RDMSR": [
        "#VE"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x080E",
        "Last": "0x080E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0810",
        "Last": "0x0817",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_X2APIC_ISRx",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0818",
        "Last": "0x081F",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_X2APIC_TMRx",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0820",
        "Last": "0x0827",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_X2APIC_IRRx",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0829",
        "Last": "0x082E",
        "Size": "0x6"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0831",
        "Last": "0x0831",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0839",
        "Last": "0x0839",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_CUR_COUNT",
      "On RDMSR": [
        "#VE"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x083B",
        "Last": "0x083D",
        "Size": "0x3"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x083F",
        "Last": "0x083F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_X2APIC_SELF_IPI",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0840",
        "Last": "0x087F",
        "Size": "0x40"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0880",
        "Last": "0x08BF",
        "Size": "0x40"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x08C0",
        "Last": "0x08FF",
        "Size": "0x40"
      },
      "MSR Architectural Name": "Reserved for xAPIC MSRs",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0980",
        "Last": "0x0980",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0981",
        "Last": "0x0981",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TME_CAPABILITY",
      "On RDMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0982",
        "Last": "0x0982",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TME_ACTIVATE",
      "On RDMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0983",
        "Last": "0x0983",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TME_EXCLUDE_MASK",
      "On RDMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0984",
        "Last": "0x0984",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TME_EXCLUDE_BASE",
      "On RDMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ],
      "On WRMSR": [
        "Inject_GP_or_VE (~virt. CPUID(7,0).ECX[13])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0985",
        "Last": "0x0985",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_RR",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0986",
        "Last": "0x0986",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_HANDLER",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0987",
        "Last": "0x0987",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_STACKADJUST",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0988",
        "Last": "0x0988",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_MISC",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0989",
        "Last": "0x0989",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_PD",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098A",
        "Last": "0x098A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UINTR_TT",
      "On RDMSR": [
        "Inject_GP(~XFAM[14])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[14])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098B",
        "Last": "0x098B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR-High-ADDR15",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098C",
        "Last": "0x098C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR15",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098D",
        "Last": "0x098D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR-Low-ADDR16",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098E",
        "Last": "0x098E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR-High-ADDR16",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x098F",
        "Last": "0x098F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPRR_EN_ATTR16",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0990",
        "Last": "0x0990",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0991",
        "Last": "0x0991",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x09A0",
        "Last": "0x09A3",
        "Size": "0x4"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x09C0",
        "Last": "0x09C3",
        "Size": "0x4"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x09E0",
        "Last": "0x09E7",
        "Size": "0x8"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x09F0",
        "Last": "0x09F7",
        "Size": "0x8"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x09FD",
        "Last": "0x09FD",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0A80",
        "Last": "0x0AFF",
        "Size": "0x80"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0B00",
        "Last": "0x0B7F",
        "Size": "0x80"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0B80",
        "Last": "0x0BFF",
        "Size": "0x80"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C80",
        "Last": "0x0C80",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_DEBUG_INTERFACE",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C81",
        "Last": "0x0C81",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_L3_QOS_CFG",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C82",
        "Last": "0x0C82",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_L2_QOS_CFG",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C8D",
        "Last": "0x0C8D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_QM_EVTSEL",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C8E",
        "Last": "0x0C8E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_QM_CTR",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C8F",
        "Last": "0x0C8F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PQR_ASSOC",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[12])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0C90",
        "Last": "0x0D0F",
        "Size": "0x80"
      },
      "MSR Architectural Name": "IA32_L3_QOS_MASK_x",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D10",
        "Last": "0x0D4F",
        "Size": "0x40"
      },
      "MSR Architectural Name": "IA32_L2_QOS_MASK_x",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D50",
        "Last": "0x0D8F",
        "Size": "0x40"
      },
      "MSR Architectural Name": "IA32_L2_QOS_Ext_BW_Thrtl_x",
      "On RDMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(~virt. CPUID(7,0).EBX[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D90",
        "Last": "0x0D90",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_BNDCFGS",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D91",
        "Last": "0x0D91",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D92",
        "Last": "0x0D92",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0D93",
        "Last": "0x0D93",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PASID",
      "On RDMSR": [
        "#GP(0)"
      ],
      "On WRMSR": [
        "#GP(0)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DA0",
        "Last": "0x0DA0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_XSS",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "if invalid or does not match XFAM",
        "    #GP(0)",
        "else",
        "    Write to CPU"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DB0",
        "Last": "0x0DB0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PKG_HDC_CTL",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DB1",
        "Last": "0x0DB1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_PM_CTL1",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DB2",
        "Last": "0x0DB2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_THREAD_STALL",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x0DC0",
        "Last": "0x0DFF",
        "Size": "0x40"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1000",
        "Last": "0x1000",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_MPX_LAX",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1200",
        "Last": "0x12FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_INFO",
      "On RDMSR": [
        "Inject_GP(~XFAM[15])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1309",
        "Last": "0x130B",
        "Size": "0x3"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1400",
        "Last": "0x1400",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SEAMRR_BASE",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1401",
        "Last": "0x1401",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SEAMRR_MASK",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1402",
        "Last": "0x1402",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_SEAM_EXTEND",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x14C1",
        "Last": "0x14C8",
        "Size": "0x8"
      },
      "MSR Architectural Name": "IA32_RELOAD_PMCx",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x14CE",
        "Last": "0x14CE",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LBR_CTL",
      "On RDMSR": [
        "Inject_GP(~XFAM[15])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x14CF",
        "Last": "0x14CF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LBR_DEPTH",
      "On RDMSR": [
        "Inject_GP(~XFAM[15])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1500",
        "Last": "0x15FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_x_FROM_IP",
      "On RDMSR": [
        "Inject_GP(~XFAM[15])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1600",
        "Last": "0x16FF",
        "Size": "0x100"
      },
      "MSR Architectural Name": "IA32_LBR_x_TO_IP",
      "On RDMSR": [
        "Inject_GP(~XFAM[15])"
      ],
      "On WRMSR": [
        "Inject_GP(~XFAM[15])"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x17D0",
        "Last": "0x17D0",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HW_FEEDBACK_PTR",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x17D1",
        "Last": "0x17D1",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HW_FEEDBACK_CONFIG",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x17D2",
        "Last": "0x17D2",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_THREAD_FEEDBACK_CHAR",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x17D4",
        "Last": "0x17D4",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HW_FEEDBACK_THREAD_CONFIG",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x17DA",
        "Last": "0x17DA",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_HRESET_ENABLE",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1900",
        "Last": "0x1900",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1901",
        "Last": "0x1901",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1902",
        "Last": "0x1902",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1903",
        "Last": "0x1903",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1904",
        "Last": "0x1904",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1905",
        "Last": "0x1905",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1906",
        "Last": "0x1906",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1907",
        "Last": "0x1907",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1908",
        "Last": "0x1908",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1909",
        "Last": "0x1909",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190A",
        "Last": "0x190A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190B",
        "Last": "0x190B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190C",
        "Last": "0x190C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190D",
        "Last": "0x190D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190E",
        "Last": "0x190E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x190F",
        "Last": "0x190F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1910",
        "Last": "0x1910",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1911",
        "Last": "0x1911",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1912",
        "Last": "0x1912",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1913",
        "Last": "0x1913",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1914",
        "Last": "0x1914",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1915",
        "Last": "0x1915",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1916",
        "Last": "0x1916",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1917",
        "Last": "0x1917",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1918",
        "Last": "0x1918",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1919",
        "Last": "0x1919",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191A",
        "Last": "0x191A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191B",
        "Last": "0x191B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191C",
        "Last": "0x191C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191D",
        "Last": "0x191D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191E",
        "Last": "0x191E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x191F",
        "Last": "0x191F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1920",
        "Last": "0x1920",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1921",
        "Last": "0x1921",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1922",
        "Last": "0x1922",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1923",
        "Last": "0x1923",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1924",
        "Last": "0x1924",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1925",
        "Last": "0x1925",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1926",
        "Last": "0x1926",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1927",
        "Last": "0x1927",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1980",
        "Last": "0x1980",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1981",
        "Last": "0x1981",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1982",
        "Last": "0x1982",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1983",
        "Last": "0x1983",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1984",
        "Last": "0x1984",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1985",
        "Last": "0x1985",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1986",
        "Last": "0x1986",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1987",
        "Last": "0x1987",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1988",
        "Last": "0x1988",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1989",
        "Last": "0x1989",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198A",
        "Last": "0x198A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198B",
        "Last": "0x198B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198C",
        "Last": "0x198C",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198D",
        "Last": "0x198D",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198E",
        "Last": "0x198E",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x198F",
        "Last": "0x198F",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1990",
        "Last": "0x1990",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1991",
        "Last": "0x1991",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1992",
        "Last": "0x1992",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1993",
        "Last": "0x1993",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1994",
        "Last": "0x1994",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1995",
        "Last": "0x1995",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1996",
        "Last": "0x1996",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1997",
        "Last": "0x1997",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1998",
        "Last": "0x1998",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1999",
        "Last": "0x1999",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x199A",
        "Last": "0x199A",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x199B",
        "Last": "0x199B",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0x1B01",
        "Last": "0x1B01",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_UARCH_MISC_CTL",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000080",
        "Last": "0xC0000080",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_EFER",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "If TD Partitioning is supported:",
        "- Ignore read-only bit LMA (10)",
        "- Allow update of bit SCE (0)",
        "- For L2, allow update of bit LME (8)",
        "- #VE(UNSUPPORTED_FEATURE) on any other change",
        "Else:",
        "- #VE(UNSUPPORTED_FEATURE)"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000081",
        "Last": "0xC0000081",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_STAR",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000082",
        "Last": "0xC0000082",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_LSTAR",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000084",
        "Last": "0xC0000084",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FMASK",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000100",
        "Last": "0xC0000100",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_FSBASE",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000101",
        "Last": "0xC0000101",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_GSBASE",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000102",
        "Last": "0xC0000102",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_KERNEL_GS_BASE",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xC0000103",
        "Last": "0xC0000103",
        "Size": "0x1"
      },
      "MSR Architectural Name": "IA32_TSC_AUX",
      "On RDMSR": [
        "Native"
      ],
      "On WRMSR": [
        "Native"
      ]
    },
    {
      "MSR Index Range": {
        "First": "0xFFFFFFFF",
        "Last": "0xFFFFFFFF",
        "Size": "0x1"
      },
      "MSR Architectural Name": "Reserved",
      "On RDMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ],
      "On WRMSR": [
        "inject_GP_or_VE(TD_CTLS.REDUCE_VE)"
      ]
    }
  ]
}