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<instructionsection id="SUB_ADR" title="SUB (immediate, from PC) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="SUB"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="mnemonic" value="ADR"/>
  </docvars>
  <heading>SUB (immediate, from PC)</heading>
  <desc>
    <brief>
      <para>Subtract from PC</para>
    </brief>
    <authored>
      <para>Subtract from PC subtracts an immediate value from the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register.  Arm recommends that, where possible, software avoids using this alias.</para>
    </authored>
  </desc>
  <aliasto refiform="adr.xml" iformid="ADR">ADR</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A2" oneof="2" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="ADR"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A32.dp.dpimm.intdp2reg_imm.ADR_A2.SUB" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" psbits="xxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"/>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_A2" oneofinclass="1" oneof="2" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="ADR"/>
          <docvar key="alias_mnemonic" value="SUB"/>
        </docvars>
        <asmtemplate><text>SUB{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="For the &quot;A2&quot; variant: is the general-purpose destination register, encoded in the &quot;Rd&quot; field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see x[Pseudocode description of operations on the AArch32 general-purpose registers and the PC](BEICJFEH)." link="Rd__23">&lt;Rd&gt;</a><text>, PC, #</text><a hover="An immediate value. See x[Modified immediate constants in A32 instructions](BABHDAJF) for the range of values." link="const__15">&lt;const&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_A2">ADR</a><text>{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." href="adr_a32.xml#cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." href="adr_a32.xml#qw_option">&lt;q&gt;</a><text>}  </text><a hover="For the &quot;A2&quot; variant: is the general-purpose destination register, encoded in the &quot;Rd&quot; field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see x[Pseudocode description of operations on the AArch32 general-purpose registers and the PC](BEICJFEH)." href="adr_a32.xml#Rd__23">&lt;Rd&gt;</a><text>, </text><a hover="For the &quot;A1&quot; and &quot;A2&quot; variants: the label of an instruction or literal data item whose address is to be loaded into &lt;Rd&gt;. The assembler calculates the required value of the offset from the Align(PC, 4) value of the ADR instruction to this label." href="adr_a32.xml#imm__22">&lt;label&gt;</a></asmtemplate>
          <aliascond>imm12 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="2" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="ADR"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.imm.dpint_imms.ADR_T2.SUB" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="1" name="i" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="o1" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="22" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="20" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" psbits="xxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"/>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"/>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_T2" oneofinclass="1" oneof="2" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="ADR"/>
          <docvar key="alias_mnemonic" value="SUB"/>
        </docvars>
        <asmtemplate><text>SUB{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="For the &quot;T2&quot; variant: is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd__25">&lt;Rd&gt;</a><text>, PC, #</text><a hover="Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the &quot;i:imm3:imm8&quot; field." link="imm12">&lt;imm12&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_T2">ADR</a><text>{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." href="adr_a32.xml#cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." href="adr_a32.xml#qw_option">&lt;q&gt;</a><text>}  </text><a hover="For the &quot;T2&quot; variant: is the general-purpose destination register, encoded in the &quot;Rd&quot; field." href="adr_a32.xml#Rd__25">&lt;Rd&gt;</a><text>, </text><a hover="For the &quot;T2&quot; and &quot;T3&quot; variants: the label of an instruction or literal data item whose address is to be loaded into &lt;Rd&gt;. The assembler calculates the required value of the offset from the Align(PC, 4) value of the ADR instruction to this label." href="adr_a32.xml#i_imm3_imm8__4">&lt;label&gt;</a></asmtemplate>
          <aliascond>i :: imm3 :: imm8 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="cond__2">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="Rd__23">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For the "A2" variant: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="2">
      <symbol link="Rd__25">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For the "T2" variant: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="const__15">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="1">
      <symbol link="imm12">&lt;imm12&gt;</symbol>
      <account encodedin="(i :: imm3 :: imm8)">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
