VUZP (alias) Vector Unzip Vector Unzip de-interleaves the elements of two vectors. VTRN It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 VUZP{<c>}{<q>}.32 <Dd>, <Dm> VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> Never 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 VUZP{<c>}{<q>}.32 <Dd>, <Dm> VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> Never <c> For the "A1 64-bit SIMD vector" variant: see Standard assembler syntax fields. This encoding must be unconditional. <c> For the "T1 64-bit SIMD vector" variant: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dm> Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. 2026-03-12 12:23:09 2025-09_rel_asl1