POP (multiple registers) Pop Multiple Registers from Stack Pop Multiple Registers from Stack loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. LDM, LDMIA, LDMFD It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 ) . != 1111 1 0 0 0 1 0 1 1 1 1 0 1 POP{<c>}{<q>} <registers> LDM{IA}{<c>}{<q>} SP!, <registers> BitCount(register_list) > 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 POP{<c>}{<q>} <registers> POP{<c>}.W <registers> LDM{IA}{<c>}.W SP!, <registers> BitCount(P :: M :: register_list) > 1 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <registers> For the "A1" variant: is a list of two or more registers to be loaded, separated by commas and surrounded by { and }. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. If the SP is in the list, the value of the SP after such an instruction is UNKNOWN. The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Arm deprecates the use of this instruction with both the LR and the PC in the list. <registers> For the "T2" variant: is a list of two or more registers to be loaded, separated by commas and surrounded by { and }. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0. The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. If the PC is in the list: The LR must not be in the list. The instruction must be either outside any IT block, or the last instruction in an IT block. 2026-03-26 20:27:25 2026-03_rel