AMCG1IDR

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AMCG1IDR_EL0, Activity Monitors Counter Group 1 Identification Register

Purpose

Defines which auxiliary counters are implemented, and which of them have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMCG1IDR_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:32]

AMEVCNTOFF1<n>_EL2, bit [n+16], for n = 15 to 0

Indicates which implemented auxiliary counters have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

AMEVCNTOFF1<n>_EL2	Meaning
0b0	AMEVCNTR1<n>_EL0 does not have an offset, or is not implemented.
0b1	The offset AMEVCNTVOFF1<n>_EL2 is implemented for AMEVCNTR1<n>_EL0.

AMEVCNTR1<n>_EL0, bit [n], for n = 15 to 0

Indicates which auxiliary counters AMEVCNTR1<n>_EL0 are implemented.

AMEVCNTR1<n>_EL0	Meaning
0b0	AMEVCNTR1<n>_EL0 is not implemented.
0b1	AMEVCNTR1<n>_EL0 is implemented.

Accessing AMCG1IDR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMCG1IDR_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1101	0b0010	0b110

if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif AMUSERENR_EL0().EN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCG1IDR_EL0(); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
AMEVCNTOFF115_EL2	AMEVCNTOFF114_EL2	AMEVCNTOFF113_EL2	AMEVCNTOFF112_EL2	AMEVCNTOFF111_EL2	AMEVCNTOFF110_EL2	AMEVCNTOFF19_EL2	AMEVCNTOFF18_EL2	AMEVCNTOFF17_EL2	AMEVCNTOFF16_EL2	AMEVCNTOFF15_EL2	AMEVCNTOFF14_EL2	AMEVCNTOFF13_EL2	AMEVCNTOFF12_EL2	AMEVCNTOFF11_EL2	AMEVCNTOFF10_EL2	AMEVCNTR115_EL0	AMEVCNTR114_EL0	AMEVCNTR113_EL0	AMEVCNTR112_EL0	AMEVCNTR111_EL0	AMEVCNTR110_EL0	AMEVCNTR19_EL0	AMEVCNTR18_EL0	AMEVCNTR17_EL0	AMEVCNTR16_EL0	AMEVCNTR15_EL0	AMEVCNTR14_EL0	AMEVCNTR13_EL0	AMEVCNTR12_EL0	AMEVCNTR11_EL0	AMEVCNTR10_EL0