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AMEVCNTVOFF1<n>_EL2

AMEVCNTVOFF1<n>_EL2, Activity Monitors Event Counter Virtual Offset Registers 1, n = 0 - 15

The AMEVCNTVOFF1<n>_EL2 characteristics are:

Purpose

Holds the 64-bit virtual offset for auxiliary activity monitor events.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMEVCNTVOFF1<n>_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

AMEVCNTVOFF1<n>_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
VOffset
VOffset

VOffset, bits [63:0]

Virtual offset.

The reset behavior of this field is:

Accessing AMEVCNTVOFF1<n>_EL2

Note

AMCG1IDR_EL0 identifies which auxiliary activity monitor event counters have a corresponding virtual offset implemented.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMEVCNTVOFF1<m>_EL2 ; Where m = 0-15

op0op1CRnCRmop2
0b110b1000b11010b101:m[3]m[2:0]

let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif m >= NUM_AMU_CG1_MONITORS then Undefined(); elsif !IsG1ActivityMonitorOffsetImplemented(m) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0xA80 + (8 * m)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().AMVOFFEN == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().AMVOFFEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVCNTVOFF1_EL2(m); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMEVCNTVOFF1_EL2(m); end;

MSR AMEVCNTVOFF1<m>_EL2, <Xt> ; Where m = 0-15

op0op1CRnCRmop2
0b110b1000b11010b101:m[3]m[2:0]

let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif m >= NUM_AMU_CG1_MONITORS then Undefined(); elsif !IsG1ActivityMonitorOffsetImplemented(m) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0xA80 + (8 * m)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().AMVOFFEN == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().AMVOFFEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AMEVCNTVOFF1_EL2(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then AMEVCNTVOFF1_EL2(m) = X{64}(t); end;


2026-03-12 12:23:09, 2025-09_rel_asl1

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