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CNTPCT_EL0

CNTPCT_EL0, Counter-timer Physical Count Register

The CNTPCT_EL0 characteristics are:

Purpose

Reads of CNTPCT_EL0 return the 64-bit physical count value minus a physical offset.

Configuration

AArch64 System register CNTPCT_EL0 bits [63:0] are architecturally mapped to AArch32 System register CNTPCT[63:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to CNTPCT_EL0 are UNDEFINED.

All reads to the CNTPCT_EL0 occur in program order relative to reads to CNTPCTSS_EL0 or CNTPCT_EL0.

Attributes

CNTPCT_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
PhysicalCount
PhysicalCount

PhysicalCount, bits [63:0]

Physical count value.

If the access is not trapped and all of the following are true, then reads of CNTPCT_EL0 from EL0 or EL1 return (PhysicalCountInt<63:0> - CNTPOFF_EL2<63:0>):

Otherwise, reads of CNTPCT_EL0 return PhysicalCountInt<63:0>.

PhysicalCountInt is defined by 'The Physical Counter'.

The reset behavior of this field is:

Accessing CNTPCT_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTPCT_EL0

op0op1CRnCRmop2
0b110b0110b11100b00000b001

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PCTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' && !ELIsInHost(EL0) then X{64}(t) = PhysicalCountInt() - CNTPOFF_EL2(); else X{64}(t) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' then X{64}(t) = PhysicalCountInt() - CNTPOFF_EL2(); else X{64}(t) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL2 then X{64}(t) = PhysicalCountInt(); elsif PSTATE.EL == EL3 then X{64}(t) = PhysicalCountInt(); end;


2026-03-12 12:23:09, 2025-09_rel_asl1

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