CNTPCTSS

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CNTPCTSS_EL0, Counter-timer Self-Synchronized Physical Count Register

Purpose

Configuration

AArch64 System register CNTPCTSS_EL0 bits [63:0] are architecturally mapped to AArch32 System register CNTPCTSS[63:0].

This register is present only when FEAT_ECV is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to CNTPCTSS_EL0 are UNDEFINED.

All reads to the CNTPCTSS_EL0 occur in program order relative to reads to CNTPCT_EL0 or CNTPCTSS_EL0.

This register is a view of the CNTPCT_EL0 register for which reads appear to occur in program order relative to other instructions, without the need for any explicit synchronization. Reads of this register return a value consistent with the counter not being read until the read instruction is known to be non-speculative.

Attributes

Field descriptions

Physical count value.

If the access is not trapped and all of the following are true, then reads of CNTPCTSS_EL0 from EL0 or EL1 return (PhysicalCountInt<63:0> - CNTPOFF_EL2<63:0>):

EL2 is implemented and enabled in the current Security state.
CNTHCTL_EL2.ECV is 1.
SCR_EL3.ECVEn is 1.
The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.

Otherwise, reads of CNTPCTSS_EL0 return PhysicalCountInt<63:0>.

PhysicalCountInt is defined by 'The Physical Counter'.

SSPhysicalCount, bits [63:0]

Accessing CNTPCTSS_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTPCTSS_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0000	0b101

if !(IsFeatureImplemented(FEAT_ECV) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PCTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' && !ELIsInHost(EL0) then X{64}(t) = PhysicalCountInt() - CNTPOFF_EL2(); else X{64}(t) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' then X{64}(t) = PhysicalCountInt() - CNTPOFF_EL2(); else X{64}(t) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL2 then X{64}(t) = PhysicalCountInt(); elsif PSTATE.EL == EL3 then X{64}(t) = PhysicalCountInt(); end;

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SSPhysicalCount
SSPhysicalCount