DC GVA, Data Cache set Allocation Tag by VA

Executing DC GVA

When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous Data Abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is not set.

A DC GVA instruction to any type of Device memory is CONSTRAINED UNPREDICTABLE between:

• Not modifying Allocation tags at the specified addresses.
• Generating an Alignment Fault determined by the memory type.

This instruction applies to Normal memory regardless of cacheability attributes.

This instruction behaves as a set of stores to each Allocation Tag within the block being accessed, and so it:

• Generates a Permission fault if the translation system does not permit writes to the locations.
• Requires the same considerations for ordering and the management of coherency as any other store instructions.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

op0	op1	CRn	CRm	op2
0b01	0b011	0b0111	0b0100	0b011

if !IsFeatureImplemented(FEAT_MTE) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1().DZE == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCZVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2().DZE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_Tag); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCZVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_Tag); end; elsif PSTATE.EL == EL2 then AArch64_MemZero(X{64}(t), CacheType_Tag); elsif PSTATE.EL == EL3 then AArch64_MemZero(X{64}(t), CacheType_Tag); end;