DCZID_EL0

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

DCZID_EL0, Data Cache Zero ID Register

Purpose

Indicates the block size that is written with byte values of 0 by the DC ZVA (Data Cache Zero by Address) System instruction.

If FEAT_MTE is implemented, this register indicates the granularity at which the DC GVA and DC GZVA instructions write.

Configuration

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DCZID_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:5]

DZP, bit [4]

Data Zero Prohibited. This field indicates whether use of DC ZVA instructions is permitted or prohibited.

If FEAT_MTE is implemented, this field indicates whether use of the DC GVA and DC GZVA instructions are permitted or prohibited.

DZP	Meaning
0b0	Instructions are permitted.
0b1	Instructions are prohibited.

The value read from this field is governed by the current Exception level and the values of the following fields:

The Effective value of HCR_EL2.TDZ.
When the Effective value of HCR_EL2.{E2H, TGE} != '11', SCTLR_EL1.DZE.
When the Effective value of HCR_EL2.{E2H, TGE} == '11', SCTLR_EL2.DZE.

BS, bits [3:0]

Log₂ of the block size in words written by a DC ZVA instruction. The maximum size supported is 2KB, indicated by value 0b1001.

If FEAT_MTE2 is implemented, then this field determines the block size written by a DC GVA or DC GZVA instruction and the minimum size supported is 16 bytes, indicated by value 0b0010.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing DCZID_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DCZID_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b0000	0b0000	0b111

if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().DCZID_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = DCZID_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().DCZID_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = DCZID_EL0(); end; elsif PSTATE.EL == EL2 then X{64}(t) = DCZID_EL0(); elsif PSTATE.EL == EL3 then X{64}(t) = DCZID_EL0(); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																											DZP	BS