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MPAMBW3_EL3
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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Proprietary Notice

MPAMBW3_EL3, MPAM PE-side Maximum-bandwidth Control Register (EL3)

The MPAMBW3_EL3 characteristics are:

Purpose

Enables software to configure a maximum fraction of memory bandwidth that the PE is permitted to use when executing at EL3 with its current PARTID.

Configuration

This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented. Otherwise, direct accesses to MPAMBW3_EL3 are UNDEFINED.

Attributes

MPAMBW3_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
HW_SCALE_ENABLEENABLEDHARDLIMRES0nTRAPLOWERRES0
MAX

HW_SCALE_ENABLE, bit [63]
When MPAMBWIDR_EL1.HAS_HW_SCALE == 1:

Enables hardware bandwidth scaling of the MPAMBW3_EL3.MAX value.

HW_SCALE_ENABLEMeaning
0b0

PE-side memory bandwidth control hardware scaling in EL3 is disabled.

0b1

PE-side memory bandwidth control hardware scaling in EL3 is enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ENABLED, bit [62]

Enables the PE-side memory bandwidth control when in EL3.

ENABLEDMeaning
0b0

The PE-side memory bandwidth control in EL3 is disabled.

0b1

The PE-side memory bandwidth control in EL3 is enabled.

The reset behavior of this field is:

HARDLIM, bit [61]

PE-side Maximum Bandwidth Limit Behavior Selection.

HARDLIMMeaning
0b0

Soft limit: when MPAMBW3_EL3.MAX bandwidth is exceeded, the PE is unregulated unless the downstream memory path is saturated. It is IMPLEMENTATION DEFINED how hardware determines when the downstream memory path is saturated.

0b1

Hard limit: when MPAMBW3_EL3.MAX bandwidth is exceeded, the PE does not use any more bandwidth until the memory bandwidth for the PE falls below MPAMBW3_EL3.MAX.

The reset behavior of this field is:

Accessing this field has the following behavior:

Bits [60:50]

Reserved, RES0.

nTRAPLOWER, bit [49]

Traps accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from any lower EL to EL3.

nTRAPLOWERMeaning
0b0

Accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from EL1 are trapped to EL3 with EC syndrome value 0x18.

0b1

Accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from EL1 are not trapped by this mechanism.

Note

This trap is higher priority than any of the traps controlled by MPAM _EL2 registers.

The reset behavior of this field is:

Bits [48:32]

Reserved, RES0.

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 1 and MPAMBW3_EL3.HW_SCALE_ENABLE == 1

313029282726252423222120191817161514131211109876543210
MAX

MAX, bits [31:0]

Maximum memory bandwidth allocated to the PE when executing at EL3 with its current PARTID.

The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [31:16] represent the integer part of the value.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 0 or MPAMBW3_EL3.HW_SCALE_ENABLE == 0

313029282726252423222120191817161514131211109876543210
RES0MAX

Bits [31:16]

Reserved, RES0.

MAX, bits [15:0]

Maximum memory bandwidth allocated to the PE when executing at EL3 with its current PARTID.

The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing MPAMBW3_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMBW3_EL3

op0op1CRnCRmop2
0b110b1100b10100b01010b100

if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBW3_EL3(); end;

MSR MPAMBW3_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b10100b01010b100

if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then MPAMBW3_EL3() = X{64}(t); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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