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GICD_ISACTIVER<n>

GICD_ISACTIVER<n>, Interrupt Set-Active Registers, n = 0 - 31

The GICD_ISACTIVER<n> characteristics are:

Purpose

Activates the corresponding interrupt. These registers are used when saving and restoring GIC state.

Configuration

These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.

The number of implemented GICD_ISACTIVER<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

GICD_ISACTIVER0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.

Accessing GICD_ISACTIVER0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:

Register is RAZ/WI.
An UNKNOWN banked copy of the register is accessed.

Attributes

GICD_ISACTIVER<n> is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Set_active_bit31	Set_active_bit30	Set_active_bit29	Set_active_bit28	Set_active_bit27	Set_active_bit26	Set_active_bit25	Set_active_bit24	Set_active_bit23	Set_active_bit22	Set_active_bit21	Set_active_bit20	Set_active_bit19	Set_active_bit18	Set_active_bit17	Set_active_bit16	Set_active_bit15	Set_active_bit14	Set_active_bit13	Set_active_bit12	Set_active_bit11	Set_active_bit10	Set_active_bit9	Set_active_bit8	Set_active_bit7	Set_active_bit6	Set_active_bit5	Set_active_bit4	Set_active_bit3	Set_active_bit2	Set_active_bit1	Set_active_bit0

Set_active_bit<x>, bit [x], for x = 31 to 0

Adds the active state to interrupt number 32n + x. Reads and writes have the following behavior:

Set_active_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is active, or is active and pending. If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect. After a write of 1 to this bit, a subsequent read of this bit returns 1.

Set_active_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or is active and pending.

If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

On a GIC reset, this field resets to '0'.

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ISACTIVER<n> number, n, is given by n = m DIV 32.
The offset of the required GICD_ISACTIVER is (0x300 + (4*n)).
The bit number of the required group modifier bit in this register is m MOD 32.

Accessing GICD_ISACTIVER<n>

When affinity routing is enabled for the Security state of an interrupt, bits corresponding to SGIs and PPIs are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ISACTIVER0.

Bits corresponding to unimplemented interrupts are RAZ/WI.

If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.

The bit reads as one if the status of the interrupt is active or active and pending. GICD_ISPENDR<n> and GICD_ICPENDR<n> provide the pending status of the interrupt.

The effect of a write must be visible in finite time. Reading back the written value from either the Set-Active or Clear-Active registers guarantees that a deactivate from a CPU interface Ordered-after the read, will observe the effects of the write on the Active state of the interrupt.

GICD_ISACTIVER<n> can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x0300 + (4 * n)	GICD_ISACTIVER<n>

Accessible as follows:

When GICD_CTLR.DS == 0, accesses to this register are RW.
When an access is Secure, accesses to this register are RW.
When an access is Non-secure, accesses to this register are RW.

2026-03-12 12:23:09, 2025-09_rel_asl1