ATS1CPRP

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ATS1CPRP, Address Translate Stage 1 Current state PL1 Read PAN

Purpose

Performs a stage 1 address translation at PL1 and in the current Security state, where the value of PSTATE.PAN determines if a read from a location will generate a Permission fault for a privileged access.

Configuration

This instruction is present only when FEAT_AA32EL1 is implemented and FEAT_PAN2 is implemented. Otherwise, direct accesses to ATS1CPRP are UNDEFINED.

Attributes

Field descriptions

IA, bits [31:0]

Input address for translation. The resulting address can be read from the PAR.

This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.

Executing ATS1CPRP

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b0111	0b1001	0b000

if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_PAN2)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); else AArch32_AT(R(t), TranslationStage_1, EL1, ATAccess_ReadPAN); end; elsif PSTATE.EL == EL2 then AArch32_AT(R(t), TranslationStage_1, EL1, ATAccess_ReadPAN); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then AArch32_AT(R(t), TranslationStage_1, EL3, ATAccess_ReadPAN); else AArch32_AT(R(t), TranslationStage_1, EL1, ATAccess_ReadPAN); end; end;

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