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CNTPCTSS
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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External Registers
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Proprietary Notice

CNTPCTSS, Counter-timer Self-Synchronized Physical Count register

The CNTPCTSS characteristics are:

Purpose

Holds the 64-bit physical count value.

Configuration

AArch32 System register CNTPCTSS bits [63:0] are architecturally mapped to AArch64 System register CNTPCTSS_EL0[63:0].

This register is present only when FEAT_AA32 is implemented and FEAT_ECV is implemented. Otherwise, direct accesses to CNTPCTSS are UNDEFINED.

All reads to the CNTPCTSS occur in program order relative to reads to CNTPCT or CNTPCTSS.

This register is a view of the CNTPCT register for which reads appear to occur in program order relative to other instructions, without the need for any explicit synchronization. Reads of this register return a value consistent with the counter not being read until the read instruction is known to be non-speculative.

Attributes

CNTPCTSS is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
SSPhysicalCount
SSPhysicalCount

SSPhysicalCount, bits [63:0]

Self-Synchronized Physical count value.

The reset behavior of this field is:

Accessing CNTPCTSS

Accesses to this register use the following encodings in the System register encoding space:

MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

coprocCRmopc1
0b11110b11100b1000

if !(IsFeatureImplemented(FEAT_AA32) && IsFeatureImplemented(FEAT_ECV)) then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PCTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); else AArch64_AArch32SystemAccessTrap(EL1, 0x04); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && CNTKCTL().PL0PCTEN == '0' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL0) && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && CNTHCTL_EL2().EL0PCTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && CNTHCTL().PL1PCTEN == '0' then AArch32_TakeHypTrapException(0x04); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' && !ELIsInHost(EL0) then R(t, t2) = PhysicalCountInt() - CNTPOFF_EL2(); else R(t, t2) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && CNTHCTL_EL2().EL1PCTEN == '0' then AArch64_AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && CNTHCTL().PL1PCTEN == '0' then AArch32_TakeHypTrapException(0x04); else if IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') && CNTHCTL_EL2().ECV == '1' then R(t, t2) = PhysicalCountInt() - CNTPOFF_EL2(); else R(t, t2) = PhysicalCountInt(); end; end; elsif PSTATE.EL == EL2 then R(t, t2) = PhysicalCountInt(); elsif PSTATE.EL == EL3 then R(t, t2) = PhysicalCountInt(); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
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2026-03-26 20:27:25, 2026-03_rel

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