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DBGDTRTXint
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

DBGDTRTXint, Debug Data Transfer Register, Transmit

The DBGDTRTXint characteristics are:

Purpose

Transfers data from the PE to an external debugger. For example, it is used by a debug target to transfer data to the debugger. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communication Channel.

Configuration

AArch32 System register DBGDTRTXint bits [31:0] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0].

AArch32 System register DBGDTRTXint bits [31:0] are architecturally mapped to External register DBGDTRTX_EL0[31:0].

This register is present only when FEAT_AA32 is implemented. Otherwise, direct accesses to DBGDTRTXint are UNDEFINED.

Attributes

DBGDTRTXint is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
DTRTX

DTRTX, bits [31:0]

DTRTX. Writes to this register:

After the write, TXfull is set to 1.

For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'.

The reset behavior of this field is:

Accessing DBGDTRTXint

Data can be loaded from memory into this register using 'LDC (immediate)' and 'LDC (literal)'.

Accesses to this register use the following encodings in the System register encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11100b0000b00000b01010b000

if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif Halted() then Write_DBGDTR_EL0{32}(R(t)); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && MDSCR_EL1().TDCC == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); else AArch64_AArch32SystemAccessTrap(EL1, 0x05); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && DBGDSCRext().UDCCdis == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && (HCR().TGE == '1' || HDCR().[TDE,TDA] != '00') then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); else Write_DBGDTR_EL0{32}(R(t)); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); else Write_DBGDTR_EL0{32}(R(t)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x05); else Write_DBGDTR_EL0{32}(R(t)); end; elsif PSTATE.EL == EL3 then if PSTATE.M != M32_Monitor && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); else Write_DBGDTR_EL0{32}(R(t)); end; end;

LDC{<c>}{<q>} <coproc>, <CRd>, <addressing_mode>

coprocCRd
0b11100b0101

if !IsFeatureImplemented(FEAT_AA32) then Undefined(); elsif Halted() then Write_DBGDTR_EL0{32}(MemA{32}(address)); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && MDSCR_EL1().TDCC == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x06); else AArch64_AArch32SystemAccessTrap(EL1, 0x06); end; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && DBGDSCRext().UDCCdis == '1' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x06); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x06); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && IsFeatureImplemented(FEAT_FGT) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x06); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_AArch32SystemAccessTrap(EL2, 0x06); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && (HCR().TGE == '1' || HDCR().[TDE,TDA] != '00') then AArch32_TakeHypTrapException(0x06); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); else Write_DBGDTR_EL0{32}(MemA{32}(address)); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x06); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TDCC == '1' then AArch32_TakeHypTrapException(0x06); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().[TDE,TDA] != '00' then AArch64_AArch32SystemAccessTrap(EL2, 0x06); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().[TDE,TDA] != '00' then AArch32_TakeHypTrapException(0x06); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); else Write_DBGDTR_EL0{32}(MemA{32}(address)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TDA == '1' then AArch64_AArch32SystemAccessTrap(EL3, 0x06); else Write_DBGDTR_EL0{32}(MemA{32}(address)); end; elsif PSTATE.EL == EL3 then if PSTATE.M != M32_Monitor && SDCR().TDCC == '1' then AArch32_TakeMonitorTrapException(); else Write_DBGDTR_EL0{32}(MemA{32}(address)); end; end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-26 20:27:25, 2026-03_rel

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