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DCCIMVAC
AArch32 Registers
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DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC

The DCCIMVAC characteristics are:

Purpose

Clean and Invalidate data or unified cache line by virtual address to PoC.

Configuration

AArch32 System instruction DCCIMVAC performs the same function as AArch64 System instruction DC CIVAC.

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to DCCIMVAC are UNDEFINED.

Attributes

DCCIMVAC is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
VA

VA, bits [31:0]

Virtual address to use. No alignment restrictions apply to this VA.

Executing DCCIMVAC

Execution of this instruction might require an address translation from VA to PA, and that translation might fault.

For more information about faults, see 'Permission fault'.

For more information about data cache maintenance instructions, see 'AArch32 data cache maintenance instructions (DC*)'.

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01110b11100b001

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if !AArch32_CanTrapDC(CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TPCP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TPC == '1' then AArch32_TakeHypTrapException(0x03); else if AArch32_TreatDCAsNOP(CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL2 then if !AArch32_CanTrapDC(CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else if AArch32_TreatDCAsNOP(CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL3 then if AArch32_TreatDCAsNOP(CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end;

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2026-03-26 20:27:25, 2026-03_rel

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