ICIALLU

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ICIALLU, Instruction Cache Invalidate All to PoU

Purpose

Invalidate all instruction caches of the PE executing the instruction to the Point of Unification. If branch predictors are architecturally visible, also flush branch predictors.

Configuration

AArch32 System instruction ICIALLU performs the same function as AArch64 System instruction IC IALLU.

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to ICIALLU are UNDEFINED.

Attributes

Field descriptions

Executing ICIALLU

The PE ignores the value of <Rt>. Software does not have to write a value to this register before issuing this instruction.

When HCR.FB is 1, at Non-secure EL1 this instruction executes as a ICIALLUIS.

The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see the relevant instruction in the Pseudocode for AArch32 operation.

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b0111	0b0101	0b000

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if !AArch32_CanTrapIC(CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TPU == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TOCU == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TPU == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR2().TOCU == '1' then AArch32_TakeHypTrapException(0x03); else if AArch32_TreatICAsNOP(CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch32_IC(CacheOpScope_ALLU); end; end; elsif PSTATE.EL == EL2 then if !AArch32_CanTrapIC(CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else if AArch32_TreatICAsNOP(CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch32_IC(CacheOpScope_ALLU); end; end; elsif PSTATE.EL == EL3 then if AArch32_TreatICAsNOP(CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch32_IC(CacheOpScope_ALLU); end; end;