AT S1E1WP

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AT S1E1WP, Address Translate Stage 1 EL1 Write PAN

Purpose

Performs a stage 1 address translation, where the value of PSTATE.PAN determines if a write to a location will generate a Permission fault for a privileged access, using the following translation regime:

When FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is UNDEFINED at EL3.

Configuration

This instruction is present only when FEAT_PAN2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to AT S1E1WP are UNDEFINED.

Attributes

Field descriptions

IA, bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing AT S1E1WP

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

AT S1E1WP, <Xt>

op0	op1	CRn	CRm	op2
0b01	0b000	0b0111	0b1001	0b001

if !(IsFeatureImplemented(FEAT_PAN2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().AT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().ATS1E1WP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_WritePAN); end; elsif PSTATE.EL == EL2 then AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_WritePAN); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NS() == '0' && EffectiveSCR_EL3_NSE() == '1' then Undefined(); else AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_WritePAN); end; end;

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