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BRBFCR_EL1

BRBFCR_EL1, Branch Record Buffer Function Control Register

The BRBFCR_EL1 characteristics are:

Purpose

Functional controls for the Branch Record Buffer.

Configuration

This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBFCR_EL1 are UNDEFINED.

Attributes

BRBFCR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0BANKRES0CONDDIRDIRCALLINDCALLRTNINDIRECTDIRECTEnIRES0PAUSEDRES0

Bits [63:30]

Reserved, RES0.

BANK, bits [29:28]

Branch record buffer bank access control.

BANKMeaning
0b00

Select branch records 0 to 31.

0b01

Select branch records 32 to 63.

All other values are reserved.

The reset behavior of this field is:

Bits [27:23]

Reserved, RES0.

CONDDIR, bit [22]

Match on conditional direct branch instructions.

CONDDIRMeaning
0b0

Do not match on conditional direct branch instructions.

0b1

Match on conditional direct branch instructions.

The reset behavior of this field is:

DIRCALL, bit [21]

Match on direct branch with link instructions.

DIRCALLMeaning
0b0

Do not match on direct branch with link instructions.

0b1

Match on direct branch with link instructions.

The reset behavior of this field is:

INDCALL, bit [20]

Match on indirect branch with link instructions.

INDCALLMeaning
0b0

Do not match on indirect branch with link instructions.

0b1

Match on indirect branch with link instructions.

The reset behavior of this field is:

RTN, bit [19]

Match on function return instructions.

RTNMeaning
0b0

Do not match on function return instructions.

0b1

Match on function return instructions.

The reset behavior of this field is:

INDIRECT, bit [18]

Match on indirect branch instructions.

INDIRECTMeaning
0b0

Do not match on indirect branch instructions.

0b1

Match on indirect branch instructions.

The reset behavior of this field is:

DIRECT, bit [17]

Match on unconditional direct branch instructions.

DIRECTMeaning
0b0

Do not match on unconditional direct branch instructions.

0b1

Match on unconditional direct branch instructions.

The reset behavior of this field is:

EnI, bit [16]

Include or exclude matches.

EnIMeaning
0b0

Include records for matches, and exclude records for non-matches.

0b1

Exclude records for matches, and include records for non-matches.

The reset behavior of this field is:

Bits [15:8]

Reserved, RES0.

PAUSED, bit [7]

Branch recording Paused status.

PAUSEDMeaning
0b0

Branch recording is not Paused.

0b1

Branch recording is Paused.

The reset behavior of this field is:

Bits [6:0]

Reserved, RES0.

Accessing BRBFCR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, BRBFCR_EL1

op0op1CRnCRmop2
0b100b0010b10010b00000b001

if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().nBRBCTL == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = BRBFCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = BRBFCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = BRBFCR_EL1(); end;

MSR BRBFCR_EL1, <Xt>

op0op1CRnCRmop2
0b100b0010b10010b00000b001

if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().nBRBCTL == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else BRBFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else BRBFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then BRBFCR_EL1() = X{64}(t); end;


2026-03-26 20:27:25, 2026-03_rel

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