CurrentEL

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

CurrentEL, Current Exception Level

Purpose

Configuration

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to CurrentEL are UNDEFINED.

Attributes

Field descriptions

Bits [63:4]

EL, bits [3:2]

Current Exception level.

EL	Meaning
0b00	EL0.
0b01	EL1.
0b10	EL2.
0b11	EL3.

When the Effective value of HCR_EL2.NV is 1, EL1 read accesses to the CurrentEL register return the value of 0b10 in this field.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to '01'.
- When the highest implemented Exception level is EL2, this field resets to '10'.
- Otherwise, this field resets to '11'.

Bits [1:0]

Accessing CurrentEL

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CurrentEL

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0010	0b010

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then X{64}(t) = Zeros{60} :: '10' :: Zeros{2}; else X{64}(t) = Zeros{60} :: PSTATE.EL :: Zeros{2}; end; elsif PSTATE.EL == EL2 then X{64}(t) = Zeros{60} :: PSTATE.EL :: Zeros{2}; elsif PSTATE.EL == EL3 then X{64}(t) = Zeros{60} :: PSTATE.EL :: Zeros{2}; end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																												EL		RES0