DBGDTRRX

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DBGDTRRX_EL0, Debug Data Transfer Register, Receive

Purpose

Transfers data from an external debugger to the PE. For example, it is used by a debugger transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communications Channel.

Configuration

AArch64 System register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0].

AArch64 System register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to External register DBGDTRRX_EL0[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DBGDTRRX_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:32]

DTRRX, bits [31:0]

DTRRX. Reads of this register:

If RXfull is 1, return the last value written to DTRRX.
If RXfull is 0, return an UNKNOWN value.

After the read, RXfull is cleared to 0.

For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing DBGDTRRX_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DBGDTRRX_EL0

op0	op1	CRn	CRm	op2
0b10	0b011	0b0000	0b0101	0b000

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() then X{32}(t) = Read_DBGDTR_EL0{32}(); elsif PSTATE.EL == EL0 then if MDSCR_EL1().TDCC == '1' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{32}(t) = Read_DBGDTR_EL0{32}(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{32}(t) = Read_DBGDTR_EL0{32}(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{32}(t) = Read_DBGDTR_EL0{32}(); end; elsif PSTATE.EL == EL3 then X{32}(t) = Read_DBGDTR_EL0{32}(); end;

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RES0
DTRRX