ERXMISC1

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ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1

Purpose

Configuration

AArch64 System register ERXMISC1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ERXMISC2[31:0].

AArch64 System register ERXMISC1_EL1 bits [63:32] are architecturally mapped to AArch32 System register ERXMISC3[31:0].

This register is present only when FEAT_RAS is implemented. Otherwise, direct accesses to ERXMISC1_EL1 are UNDEFINED.

Attributes

Field descriptions

ERRnMISC1, bits [63:0]

Accessing ERXMISC1_EL1

If ERRIDR_EL1.NUM is 0x0000 or ERRSELR_EL1.SEL is greater than or equal to ERRIDR_EL1.NUM, then one of the following occurs:

An UNKNOWN error record is selected.
ERXMISC1_EL1 is RAZ/WI.
Direct reads and writes of ERXMISC1_EL1 are NOPs.
Direct reads and writes of ERXMISC1_EL1 are UNDEFINED.

ERR<n>MISC1 describes additional constraints that also apply when ERR<n>MISC1 is accessed through ERXMISC1_EL1.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ERXMISC1_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0101	0b001

if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TERR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().ERXMISCn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERRMISC1(UInt(ERRSELR_EL1().SEL)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERRMISC1(UInt(ERRSELR_EL1().SEL)); end; elsif PSTATE.EL == EL3 then X{64}(t) = ERRMISC1(UInt(ERRSELR_EL1().SEL)); end;

MSR ERXMISC1_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0101	0b001

if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TWERR == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TERR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().ERXMISCn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SCR_EL3().TWERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ERRMISC1(UInt(ERRSELR_EL1().SEL)) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TWERR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SCR_EL3().TWERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ERRMISC1(UInt(ERRSELR_EL1().SEL)) = X{64}(t); end; elsif PSTATE.EL == EL3 then ERRMISC1(UInt(ERRSELR_EL1().SEL)) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERRnMISC1
ERRnMISC1