NZCV

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

NZCV, Condition Flags

Purpose

Configuration

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to NZCV are UNDEFINED.

Attributes

Field descriptions

Bits [63:32]

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Bits [27:0]

Accessing NZCV

The MSR (register) and MRS instructions used to access NZCV are data-independent-time instructions as described in About PSTATE.DIT.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, NZCV

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b000

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then X{64}(t) = Zeros{32} :: PSTATE.[N,Z,C,V] :: Zeros{28}; elsif PSTATE.EL == EL1 then X{64}(t) = Zeros{32} :: PSTATE.[N,Z,C,V] :: Zeros{28}; elsif PSTATE.EL == EL2 then X{64}(t) = Zeros{32} :: PSTATE.[N,Z,C,V] :: Zeros{28}; elsif PSTATE.EL == EL3 then X{64}(t) = Zeros{32} :: PSTATE.[N,Z,C,V] :: Zeros{28}; end;

MSR NZCV, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b000

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then PSTATE.[N,Z,C,V] = X{64}(t)[31:28]; elsif PSTATE.EL == EL1 then PSTATE.[N,Z,C,V] = X{64}(t)[31:28]; elsif PSTATE.EL == EL2 then PSTATE.[N,Z,C,V] = X{64}(t)[31:28]; elsif PSTATE.EL == EL3 then PSTATE.[N,Z,C,V] = X{64}(t)[31:28]; end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
N	Z	C	V	RES0