PMEVCNTR<n>

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PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30

Purpose

Configuration

AArch64 System register PMEVCNTR<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVCNTR<n>[31:0].

AArch64 System register PMEVCNTR<n>_EL0 bits [31:0] are architecturally mapped to External register PMEVCNTR<n>_EL0[31:0].

AArch64 System register PMEVCNTR<n>_EL0 bits [63:32] are architecturally mapped to External register PMEVCNTR<n>_EL0[63:32] when FEAT_PMUv3p5 is implemented.

This register is present only when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMEVCNTR<n>_EL0 are UNDEFINED.

Attributes

Field descriptions

When FEAT_PMUv3p5 is implemented:

EVCNT, bits [63:0]

Otherwise:

Bits [63:32]

EVCNT, bits [31:0]

Accessing PMEVCNTR<n>_EL0

PMEVCNTR<n>_EL0 can also be accessed by using PMXEVCNTR_EL0 with PMSELR_EL0.SEL set to the value of <n>.

If FEAT_FGT is implemented and <n> is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMEVCNTR<n>_EL0 is as follows:

If <n> is greater than or equal to the Effective value of PMCCR.EPMN, the access is UNDEFINED.
Otherwise, the access is trapped to EL2.

If FEAT_FGT is not implemented and <n> is greater than or equal to the number of accessible event counters, then reads and writes of PMEVCNTR<n>_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:

Accesses to the register are UNDEFINED.
Accesses to the register behave as RAZ/WI.
Accesses to the register execute as a NOP.
Accesses to the register behave as if <n> is an UNKNOWN value less-than-or-equal-to the index of the highest accessible event counter.
If EL2 is implemented and enabled in the current Security state, and <n> is less than the number of implemented event counters, accesses from EL1 or permitted accesses from EL0 are trapped to EL2.

Permitted reads and writes of PMEVCNTR<n>_EL0 are RAZ/WI if all of the following are true:

FEAT_PMUv3p9 is implemented.
EL0 is the current Exception level.
PMUSERENR_EL0.UEN is 1.
PMUACR_EL1.P<n> is 0.

Permitted writes of PMEVCNTR<n>_EL0 are ignored if all of the following are true:

FEAT_PMUv3p9 is implemented.
EL0 is the current Exception level.
PMUSERENR_EL0.{UEN,ER} is {1,1}.

Note

In EL0, an access is permitted if it is enabled by PMUSERENR_EL0.{UEN,ER,EN}.

If EL2 is implemented and enabled in the current Security state, in EL1 and EL0, MDCR_EL2.HPMN identifies the number of accessible event counters. Otherwise, the number of accessible event counters is the number of implemented event counters. For more information, see MDCR_EL2.HPMN.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMEVCNTR<m>_EL0 ; Where m = 0-30

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b10:m[4:3]	m[2:0]

let m:integer = UInt(CRm[1:0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m >= GetNumEventCountersSelfHosted() then if IsFeatureImplemented(FEAT_FGT) then Undefined(); else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); end; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[UEN,ER,EN] == '000') || (!IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[ER,EN] == '00') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMEVCNTRn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && PMUACR_EL1()[m] == '0' then X{64}(t) = Zeros{64}; else X{64}(t) = PMEVCNTR_EL0(m); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMEVCNTRn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMEVCNTR_EL0(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMEVCNTR_EL0(m); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMEVCNTR_EL0(m); end;

MSR PMEVCNTR<m>_EL0, <Xt> ; Where m = 0-30

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b10:m[4:3]	m[2:0]

let m:integer = UInt(CRm[1:0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m >= GetNumEventCountersSelfHosted() then if IsFeatureImplemented(FEAT_FGT) then Undefined(); else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); end; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMEVCNTRn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && (PMUACR_EL1()[m] == '0' || PMUSERENR_EL0().ER == '1') then return; else PMEVCNTR_EL0(m) = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMEVCNTRn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMEVCNTR_EL0(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMEVCNTR_EL0(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then PMEVCNTR_EL0(m) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVCNT
EVCNT

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
EVCNT