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RCWSMASK_EL1
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

RCWSMASK_EL1, Software Read Check Write Instruction Mask (EL1)

The RCWSMASK_EL1 characteristics are:

Purpose

Contains the software mask used by RCWS instructions.

Configuration

This register is present only when FEAT_THE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to RCWSMASK_EL1 are UNDEFINED.

RCWSMASK_EL1 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

RCWSMASK_EL1 is a:

Field descriptions

When FEAT_D128 is implemented:

12712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796
RCWSMASK
9594939291908988878685848382818079787776757473727170696867666564
RCWSMASK
6362616059585756555453525150494847464544434241403938373635343332
RCWSMASK
313029282726252423222120191817161514131211109876543210
RCWSMASK

RCWSMASK, bits [127:0]

Software Mask used to decide which bit-fields are writable to the 128-bit Descriptor by RCWS instructions.

If RCWSMASK_EL1 is indirectly read by 128-bit variants of RCWS instructions:

If RCWSMASK_EL1 is indirectly read by 64-bit variants of RCWS instructions:

RCWSMASK_EL1 register bits {126:125, 120:119, 114, 107:101, 90:64, 49:18, 0} are RES0.

If FEAT_S1POE is not implemented, RCWSMASK_EL1 register bits {124:121} are RES0.

If FEAT_MEC is not implemented, RCWSMASK_EL1[108] is RES0.

The reset behavior of this field is:

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RCWSMASK
RCWSMASK

RCWSMASK, bits [63:0]

Software Mask used to decide which bit-fields are writable to the 64-bit Descriptor by RCWS Instruction.

The Effective value of RCWSMASK[n] is the same as RCWSMASK_EL1[n], except as follows

RCWSMASK_EL1 register bits {49:18, 0} are RES0.

The reset behavior of this field is:

Accessing RCWSMASK_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, RCWSMASK_EL1

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nRCWSMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RCWSMASK_EL1()[63:0]; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RCWSMASK_EL1()[63:0]; end; elsif PSTATE.EL == EL3 then X{64}(t) = RCWSMASK_EL1()[63:0]; end;

MSR RCWSMASK_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nRCWSMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RCWSMASK_EL1()[63:0] = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RCWSMASK_EL1()[63:0] = X{64}(t); end; elsif PSTATE.EL == EL3 then RCWSMASK_EL1()[63:0] = X{64}(t); end;

When FEAT_D128 is implemented

MRRS <Xt>, <Xt+1>, RCWSMASK_EL1

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nRCWSMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else X{128}(t, t2) = RCWSMASK_EL1()[127:0]; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else X{128}(t, t2) = RCWSMASK_EL1()[127:0]; end; elsif PSTATE.EL == EL3 then X{128}(t, t2) = RCWSMASK_EL1()[127:0]; end;

When FEAT_D128 is implemented

MSRR RCWSMASK_EL1, <Xt>, <Xt+1>

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nRCWSMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else RCWSMASK_EL1()[127:0] = X{128}(t, t2); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else RCWSMASK_EL1()[127:0] = X{128}(t, t2); end; elsif PSTATE.EL == EL3 then RCWSMASK_EL1()[127:0] = X{128}(t, t2); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
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Index by Encoding
External Registers
External Registers by Offset
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2026-03-26 20:27:25, 2026-03_rel

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