TCR2MASK

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TCR2MASK_EL2, Extended Translation Control Masking Register (EL2)

Purpose

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TCR2MASK_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

Bits [63:19]

FNG1, bit [18]
When FEAT_ASID2 is implemented:

FNG1	Meaning
0b0	TCR2_EL2.FNG1 is writable.
0b1	TCR2_EL2.FNG1 is not writable.

Otherwise:

FNG0, bit [17]
When FEAT_ASID2 is implemented:

FNG0	Meaning
0b0	TCR2_EL2.FNG0 is writable.
0b1	TCR2_EL2.FNG0 is not writable.

Otherwise:

A2, bit [16]
When FEAT_ASID2 is implemented:

A2	Meaning
0b0	TCR2_EL2.A2 is writable.
0b1	TCR2_EL2.A2 is not writable.

Otherwise:

DisCH1, bit [15]
When FEAT_D128 is implemented:

DisCH1	Meaning
0b0	TCR2_EL2.DisCH1 is writable.
0b1	TCR2_EL2.DisCH1 is not writable.

Otherwise:

DisCH0, bit [14]
When FEAT_D128 is implemented:

DisCH0	Meaning
0b0	TCR2_EL2.DisCH0 is writable.
0b1	TCR2_EL2.DisCH0 is not writable.

Otherwise:

AMEC1, bit [13]
When FEAT_MEC is implemented:

AMEC1	Meaning
0b0	TCR2_EL2.AMEC1 is writable.
0b1	TCR2_EL2.AMEC1 is not writable.

Otherwise:

AMEC0, bit [12]
When FEAT_MEC is implemented:

AMEC0	Meaning
0b0	TCR2_EL2.AMEC0 is writable.
0b1	TCR2_EL2.AMEC0 is not writable.

Otherwise:

HAFT, bit [11]
When FEAT_HAFT is implemented:

HAFT	Meaning
0b0	TCR2_EL2.HAFT is writable.
0b1	TCR2_EL2.HAFT is not writable.

Otherwise:

PTTWI, bit [10]
When FEAT_THE is implemented:

PTTWI	Meaning
0b0	TCR2_EL2.PTTWI is writable.
0b1	TCR2_EL2.PTTWI is not writable.

Otherwise:

Bits [9:6]

D128, bit [5]
When FEAT_D128 is implemented:

D128	Meaning
0b0	TCR2_EL2.D128 is writable.
0b1	TCR2_EL2.D128 is not writable.

Otherwise:

AIE, bit [4]
When FEAT_AIE is implemented:

AIE	Meaning
0b0	TCR2_EL2.AIE is writable.
0b1	TCR2_EL2.AIE is not writable.

Otherwise:

POE, bit [3]
When FEAT_S1POE is implemented:

POE	Meaning
0b0	TCR2_EL2.POE is writable.
0b1	TCR2_EL2.POE is not writable.

Otherwise:

E0POE, bit [2]
When FEAT_S1POE is implemented:

E0POE	Meaning
0b0	TCR2_EL2.E0POE is writable.
0b1	TCR2_EL2.E0POE is not writable.

Otherwise:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PIE	Meaning
0b0	TCR2_EL2.PIE is writable.
0b1	TCR2_EL2.PIE is not writable.

Otherwise:

PnCH, bit [0]
When FEAT_THE is implemented:

PnCH	Meaning
0b0	TCR2_EL2.PnCH is writable.
0b1	TCR2_EL2.PnCH is not writable.

Otherwise:

Accessing TCR2MASK_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name TCR2MASK_EL2 or TCR2MASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCR2MASK_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0111	0b011

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCR2MASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCR2MASK_EL2(); end;

MSR TCR2MASK_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0111	0b011

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(TCR2MASK_EL2()) then Undefined(); else TCR2MASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCR2MASK_EL2() = X{64}(t); end;

MRS <Xt>, TCR2MASK_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0111	0b011

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x338); else X{64}(t) = TCR2MASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCR2MASK_EL2(); else X{64}(t) = TCR2MASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCR2MASK_EL1(); end;

MSR TCR2MASK_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0111	0b011

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x338) = X{64}(t); elsif !IsZero(TCR2MASK_EL1()) then Undefined(); else TCR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(TCR2MASK_EL2()) then Undefined(); else TCR2MASK_EL2() = X{64}(t); end; else TCR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCR2MASK_EL1() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0													FNG1	FNG0	A2	DisCH1	DisCH0	AMEC1	AMEC0	HAFT	PTTWI	RES0				D128	AIE	POE	E0POE	PIE	PnCH

TCR2MASK_EL2, Extended Translation Control Masking Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:19]

FNG1, bit [18]When FEAT_ASID2 is implemented:

Otherwise:

FNG0, bit [17]When FEAT_ASID2 is implemented:

Otherwise:

A2, bit [16]When FEAT_ASID2 is implemented:

Otherwise:

DisCH1, bit [15]When FEAT_D128 is implemented:

Otherwise:

DisCH0, bit [14]When FEAT_D128 is implemented:

Otherwise:

AMEC1, bit [13]When FEAT_MEC is implemented:

Otherwise:

AMEC0, bit [12]When FEAT_MEC is implemented:

Otherwise:

HAFT, bit [11]When FEAT_HAFT is implemented:

Otherwise:

PTTWI, bit [10]When FEAT_THE is implemented:

Otherwise:

Bits [9:6]

D128, bit [5]When FEAT_D128 is implemented:

Otherwise:

AIE, bit [4]When FEAT_AIE is implemented:

Otherwise:

POE, bit [3]When FEAT_S1POE is implemented:

Otherwise:

E0POE, bit [2]When FEAT_S1POE is implemented:

Otherwise:

PIE, bit [1]When FEAT_S1PIE is implemented:

Otherwise:

PnCH, bit [0]When FEAT_THE is implemented:

Otherwise:

Accessing TCR2MASK_EL2

MRS <Xt>, TCR2MASK_EL2

MSR TCR2MASK_EL2, <Xt>

MRS <Xt>, TCR2MASK_EL1

MSR TCR2MASK_EL1, <Xt>

FNG1, bit [18]
When FEAT_ASID2 is implemented:

FNG0, bit [17]
When FEAT_ASID2 is implemented:

A2, bit [16]
When FEAT_ASID2 is implemented:

DisCH1, bit [15]
When FEAT_D128 is implemented:

DisCH0, bit [14]
When FEAT_D128 is implemented:

AMEC1, bit [13]
When FEAT_MEC is implemented:

AMEC0, bit [12]
When FEAT_MEC is implemented:

HAFT, bit [11]
When FEAT_HAFT is implemented:

PTTWI, bit [10]
When FEAT_THE is implemented:

D128, bit [5]
When FEAT_D128 is implemented:

AIE, bit [4]
When FEAT_AIE is implemented:

POE, bit [3]
When FEAT_S1POE is implemented:

E0POE, bit [2]
When FEAT_S1POE is implemented:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PnCH, bit [0]
When FEAT_THE is implemented: