TCRMASK

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

TCRMASK_EL2, Translation Control Masking Register (EL2)

Purpose

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TCRMASK_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

Bits [63:62]

MTX1, bit [61]
When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

MTX1	Meaning
0b0	TCR_EL2.MTX1 is writable.
0b1	TCR_EL2.MTX1 is not writable.

Otherwise:

MTX0, bit [60]
When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

MTX0	Meaning
0b0	TCR_EL2.MTX0 is writable.
0b1	TCR_EL2.MTX0 is not writable.

Otherwise:

DS, bit [59]
When FEAT_LPA2 is implemented:

DS	Meaning
0b0	TCR_EL2.DS is writable.
0b1	TCR_EL2.DS is not writable.

Otherwise:

TCMA1, bit [58]
When FEAT_MTE2 is implemented:

TCMA1	Meaning
0b0	TCR_EL2.TCMA1 is writable.
0b1	TCR_EL2.TCMA1 is not writable.

Otherwise:

TCMA0, bit [57]
When FEAT_MTE2 is implemented:

TCMA0	Meaning
0b0	TCR_EL2.TCMA0 is writable.
0b1	TCR_EL2.TCMA0 is not writable.

Otherwise:

E0PD1, bit [56]
When FEAT_E0PD is implemented:

E0PD1	Meaning
0b0	TCR_EL2.E0PD1 is writable.
0b1	TCR_EL2.E0PD1 is not writable.

Otherwise:

E0PD0, bit [55]
When FEAT_E0PD is implemented:

E0PD0	Meaning
0b0	TCR_EL2.E0PD0 is writable.
0b1	TCR_EL2.E0PD0 is not writable.

Otherwise:

NFD1, bit [54]
When FEAT_SVE is implemented:

NFD1	Meaning
0b0	TCR_EL2.NFD1 is writable.
0b1	TCR_EL2.NFD1 is not writable.

Otherwise:

NFD0, bit [53]
When FEAT_SVE is implemented:

NFD0	Meaning
0b0	TCR_EL2.NFD0 is writable.
0b1	TCR_EL2.NFD0 is not writable.

Otherwise:

TBID1, bit [52]
When FEAT_PAuth is implemented:

TBID1	Meaning
0b0	TCR_EL2.TBID1 is writable.
0b1	TCR_EL2.TBID1 is not writable.

Otherwise:

TBID0, bit [51]
When FEAT_PAuth is implemented:

TBID0	Meaning
0b0	TCR_EL2.TBID0 is writable.
0b1	TCR_EL2.TBID0 is not writable.

Otherwise:

HWU162, bit [50]
When FEAT_HPDS2 is implemented:

HWU162	Meaning
0b0	TCR_EL2.HWU162 is writable.
0b1	TCR_EL2.HWU162 is not writable.

Otherwise:

HWU161, bit [49]
When FEAT_HPDS2 is implemented:

HWU161	Meaning
0b0	TCR_EL2.HWU161 is writable.
0b1	TCR_EL2.HWU161 is not writable.

Otherwise:

HWU160, bit [48]
When FEAT_HPDS2 is implemented:

HWU160	Meaning
0b0	TCR_EL2.HWU160 is writable.
0b1	TCR_EL2.HWU160 is not writable.

Otherwise:

HWU159, bit [47]
When FEAT_HPDS2 is implemented:

HWU159	Meaning
0b0	TCR_EL2.HWU159 is writable.
0b1	TCR_EL2.HWU159 is not writable.

Otherwise:

HWU062, bit [46]
When FEAT_HPDS2 is implemented:

HWU062	Meaning
0b0	TCR_EL2.HWU062 is writable.
0b1	TCR_EL2.HWU062 is not writable.

Otherwise:

HWU061, bit [45]
When FEAT_HPDS2 is implemented:

HWU061	Meaning
0b0	TCR_EL2.HWU061 is writable.
0b1	TCR_EL2.HWU061 is not writable.

Otherwise:

HWU060, bit [44]
When FEAT_HPDS2 is implemented:

HWU060	Meaning
0b0	TCR_EL2.HWU060 is writable.
0b1	TCR_EL2.HWU060 is not writable.

Otherwise:

HWU059, bit [43]
When FEAT_HPDS2 is implemented:

HWU059	Meaning
0b0	TCR_EL2.HWU059 is writable.
0b1	TCR_EL2.HWU059 is not writable.

Otherwise:

HPD1, bit [42]
When FEAT_HPDS is implemented:

HPD1	Meaning
0b0	TCR_EL2.HPD1 is writable.
0b1	TCR_EL2.HPD1 is not writable.

Otherwise:

HPD0, bit [41]
When FEAT_HPDS is implemented:

HPD0	Meaning
0b0	TCR_EL2.HPD0 is writable.
0b1	TCR_EL2.HPD0 is not writable.

Otherwise:

HD, bit [40]
When FEAT_HAFDBS is implemented:

HD	Meaning
0b0	TCR_EL2.HD is writable.
0b1	TCR_EL2.HD is not writable.

Otherwise:

HA, bit [39]
When FEAT_HAF is implemented:

HA	Meaning
0b0	TCR_EL2.HA is writable.
0b1	TCR_EL2.HA is not writable.

Otherwise:

TBI1, bit [38]

TBI0, bit [37]

AS, bit [36]

Bits [35:33]

IPS, bit [32]

Bit [31]

TG1, bit [30]

Bit [29]

SH1, bit [28]

Bit [27]

ORGN1, bit [26]

Bit [25]

IRGN1, bit [24]

EPD1, bit [23]

A1, bit [22]

Bits [21:17]

T1SZ, bit [16]

Bit [15]

TG0, bit [14]

Bit [13]

SH0, bit [12]

Bit [11]

ORGN0, bit [10]

Bit [9]

IRGN0, bit [8]

EPD0, bit [7]

Bits [6:1]

T0SZ, bit [0]

TBI1	Meaning
0b0	TCR_EL2.TBI1 is writable.
0b1	TCR_EL2.TBI1 is not writable.

TBI0	Meaning
0b0	TCR_EL2.TBI0 is writable.
0b1	TCR_EL2.TBI0 is not writable.

AS	Meaning
0b0	TCR_EL2.AS is writable.
0b1	TCR_EL2.AS is not writable.

IPS	Meaning
0b0	TCR_EL2.IPS is writable.
0b1	TCR_EL2.IPS is not writable.

TG1	Meaning
0b0	TCR_EL2.TG1 is writable.
0b1	TCR_EL2.TG1 is not writable.

SH1	Meaning
0b0	TCR_EL2.SH1 is writable.
0b1	TCR_EL2.SH1 is not writable.

ORGN1	Meaning
0b0	TCR_EL2.ORGN1 is writable.
0b1	TCR_EL2.ORGN1 is not writable.

IRGN1	Meaning
0b0	TCR_EL2.IRGN1 is writable.
0b1	TCR_EL2.IRGN1 is not writable.

EPD1	Meaning
0b0	TCR_EL2.EPD1 is writable.
0b1	TCR_EL2.EPD1 is not writable.

A1	Meaning
0b0	TCR_EL2.A1 is writable.
0b1	TCR_EL2.A1 is not writable.

T1SZ	Meaning
0b0	TCR_EL2.T1SZ is writable.
0b1	TCR_EL2.T1SZ is not writable.

TG0	Meaning
0b0	TCR_EL2.TG0 is writable.
0b1	TCR_EL2.TG0 is not writable.

SH0	Meaning
0b0	TCR_EL2.SH0 is writable.
0b1	TCR_EL2.SH0 is not writable.

ORGN0	Meaning
0b0	TCR_EL2.ORGN0 is writable.
0b1	TCR_EL2.ORGN0 is not writable.

IRGN0	Meaning
0b0	TCR_EL2.IRGN0 is writable.
0b1	TCR_EL2.IRGN0 is not writable.

EPD0	Meaning
0b0	TCR_EL2.EPD0 is writable.
0b1	TCR_EL2.EPD0 is not writable.

T0SZ	Meaning
0b0	TCR_EL2.T0SZ is writable.
0b1	TCR_EL2.T0SZ is not writable.

Accessing TCRMASK_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name TCRMASK_EL2 or TCRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCRMASK_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0111	0b010

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCRMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCRMASK_EL2(); end;

MSR TCRMASK_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0111	0b010

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(TCRMASK_EL2()) then Undefined(); else TCRMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCRMASK_EL2() = X{64}(t); end;

MRS <Xt>, TCRMASK_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0111	0b010

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x330); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCRMASK_EL2(); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCRMASK_EL1(); end;

MSR TCRMASK_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0111	0b010

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x330) = X{64}(t); elsif !IsZero(TCRMASK_EL1()) then Undefined(); else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(TCRMASK_EL2()) then Undefined(); else TCRMASK_EL2() = X{64}(t); end; else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCRMASK_EL1() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0		MTX1	MTX0	DS	TCMA1	TCMA0	E0PD1	E0PD0	NFD1	NFD0	TBID1	TBID0	HWU162	HWU161	HWU160	HWU159	HWU062	HWU061	HWU060	HWU059	HPD1	HPD0	HD	HA	TBI1	TBI0	AS	RES0			IPS
RES0	TG1	RES0	SH1	RES0	ORGN1	RES0	IRGN1	EPD1	A1	RES0					T1SZ	RES0	TG0	RES0	SH0	RES0	ORGN0	RES0	IRGN0	EPD0	RES0						T0SZ

TCRMASK_EL2, Translation Control Masking Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:62]

MTX1, bit [61]When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

Otherwise:

MTX0, bit [60]When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

Otherwise:

DS, bit [59]When FEAT_LPA2 is implemented:

Otherwise:

TCMA1, bit [58]When FEAT_MTE2 is implemented:

Otherwise:

TCMA0, bit [57]When FEAT_MTE2 is implemented:

Otherwise:

E0PD1, bit [56]When FEAT_E0PD is implemented:

Otherwise:

E0PD0, bit [55]When FEAT_E0PD is implemented:

Otherwise:

NFD1, bit [54]When FEAT_SVE is implemented:

Otherwise:

NFD0, bit [53]When FEAT_SVE is implemented:

Otherwise:

TBID1, bit [52]When FEAT_PAuth is implemented:

Otherwise:

TBID0, bit [51]When FEAT_PAuth is implemented:

Otherwise:

HWU162, bit [50]When FEAT_HPDS2 is implemented:

Otherwise:

HWU161, bit [49]When FEAT_HPDS2 is implemented:

Otherwise:

HWU160, bit [48]When FEAT_HPDS2 is implemented:

Otherwise:

HWU159, bit [47]When FEAT_HPDS2 is implemented:

Otherwise:

HWU062, bit [46]When FEAT_HPDS2 is implemented:

Otherwise:

HWU061, bit [45]When FEAT_HPDS2 is implemented:

Otherwise:

HWU060, bit [44]When FEAT_HPDS2 is implemented:

Otherwise:

HWU059, bit [43]When FEAT_HPDS2 is implemented:

Otherwise:

HPD1, bit [42]When FEAT_HPDS is implemented:

Otherwise:

HPD0, bit [41]When FEAT_HPDS is implemented:

Otherwise:

HD, bit [40]When FEAT_HAFDBS is implemented:

Otherwise:

HA, bit [39]When FEAT_HAF is implemented:

Otherwise:

TBI1, bit [38]

TBI0, bit [37]

AS, bit [36]

Bits [35:33]

IPS, bit [32]

Bit [31]

TG1, bit [30]

Bit [29]

SH1, bit [28]

Bit [27]

ORGN1, bit [26]

Bit [25]

IRGN1, bit [24]

EPD1, bit [23]

A1, bit [22]

Bits [21:17]

T1SZ, bit [16]

Bit [15]

TG0, bit [14]

Bit [13]

SH0, bit [12]

Bit [11]

ORGN0, bit [10]

Bit [9]

IRGN0, bit [8]

EPD0, bit [7]

Bits [6:1]

T0SZ, bit [0]

MTX1, bit [61]
When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

MTX0, bit [60]
When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

DS, bit [59]
When FEAT_LPA2 is implemented:

TCMA1, bit [58]
When FEAT_MTE2 is implemented:

TCMA0, bit [57]
When FEAT_MTE2 is implemented:

E0PD1, bit [56]
When FEAT_E0PD is implemented:

E0PD0, bit [55]
When FEAT_E0PD is implemented:

NFD1, bit [54]
When FEAT_SVE is implemented:

NFD0, bit [53]
When FEAT_SVE is implemented:

TBID1, bit [52]
When FEAT_PAuth is implemented:

TBID0, bit [51]
When FEAT_PAuth is implemented:

HWU162, bit [50]
When FEAT_HPDS2 is implemented:

HWU161, bit [49]
When FEAT_HPDS2 is implemented:

HWU160, bit [48]
When FEAT_HPDS2 is implemented:

HWU159, bit [47]
When FEAT_HPDS2 is implemented:

HWU062, bit [46]
When FEAT_HPDS2 is implemented:

HWU061, bit [45]
When FEAT_HPDS2 is implemented:

HWU060, bit [44]
When FEAT_HPDS2 is implemented:

HWU059, bit [43]
When FEAT_HPDS2 is implemented:

HPD1, bit [42]
When FEAT_HPDS is implemented:

HPD0, bit [41]
When FEAT_HPDS is implemented:

HD, bit [40]
When FEAT_HAFDBS is implemented:

HA, bit [39]
When FEAT_HAF is implemented: