TFSRE0

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TFSRE0_EL1, Tag Fault Status Register (EL0).

Purpose

Holds accumulated Tag Check Faults occurring at EL0 that are not taken precisely.

Configuration

This register is present only when FEAT_MTE_ASYNC is implemented. Otherwise, direct accesses to TFSRE0_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:2]

TF1, bit [1]
When FEAT_MTE_ASYNC is implemented:

Otherwise:

TF0, bit [0]
When FEAT_MTE_ASYNC is implemented:

Otherwise:

Accessing TFSRE0_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TFSRE0_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0110	0b001

if !IsFeatureImplemented(FEAT_MTE_ASYNC) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TFSRE0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TFSRE0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TFSRE0_EL1(); end;

MSR TFSRE0_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0110	0b001

if !IsFeatureImplemented(FEAT_MTE_ASYNC) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TFSRE0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TFSRE0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TFSRE0_EL1() = X{64}(t); end;

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RES0
RES0																														TF1	TF0

TFSRE0_EL1, Tag Fault Status Register (EL0).

Purpose

Configuration

Attributes

Field descriptions

Bits [63:2]

TF1, bit [1]When FEAT_MTE_ASYNC is implemented:

Otherwise:

TF0, bit [0]When FEAT_MTE_ASYNC is implemented:

Otherwise:

Accessing TFSRE0_EL1

MRS <Xt>, TFSRE0_EL1

MSR TFSRE0_EL1, <Xt>

TF1, bit [1]
When FEAT_MTE_ASYNC is implemented:

TF0, bit [0]
When FEAT_MTE_ASYNC is implemented: