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TLBI ASIDE1OS, TLBI ASIDE1OSNXS
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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Proprietary Notice

TLBI ASIDE1OS, TLBI ASIDE1OSNXS, TLB Invalidate by ASID, EL1, Outer Shareable

The TLBI ASIDE1OS, TLBI ASIDE1OSNXS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The Security state is indicated by the value of SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.

The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

This instruction is present only when FEAT_TLBIOS is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TLBI ASIDE1OS, TLBI ASIDE1OSNXS are UNDEFINED.

Attributes

TLBI ASIDE1OS, TLBI ASIDE1OSNXS is a 64-bit System instruction.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ASIDRES0
RES0

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.

If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.

Bits [47:0]

Reserved, RES0.

Executing TLBI ASIDE1OS, TLBI ASIDE1OSNXS

This system instruction is an alias of the SYS instruction.

The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBI_ASID() in the Pseudocode for AArch64 operation.

Accesses to this instruction use the following encodings in the System instruction encoding space:

TLBI ASIDE1OS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00010b010

if !(IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIASIDE1OS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); end; end;

When FEAT_XS is implemented

TLBI ASIDE1OSNXS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10010b00010b010

if !(IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIASIDE1OS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); end; end;

AArch32 Registers
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2026-03-26 20:27:25, 2026-03_rel

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