AMEVCNTR1<n>

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AMEVCNTR1<n>, Activity Monitors Event Counter Registers 1, n = 0 - 15

Purpose

Configuration

External register AMEVCNTR1<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVCNTR1<n>_EL0[63:0].

External register AMEVCNTR1<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVCNTR1<n>[31:0].

It is IMPLEMENTATION DEFINED whether AMEVCNTR1<n> is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented. Otherwise, direct accesses to AMEVCNTR1<n> are RES0.

Attributes

Field descriptions

ACNT, bits [63:0]

Auxiliary activity monitor event counter n.

Value of auxiliary activity monitor event counter n, where n is the number of this register and is a number from 0 to 15.

The reset behavior of this field is:

On an AMU reset, this field resets to the expression 0x0000000000000000.

Accessing AMEVCNTR1<n>

If <n> is greater than or equal to AMCGCR.CG1NC or FEAT_AMUv1p1 is implemented and auxiliary counter <n> is not implemented, then reads of AMEVCNTR1<n> are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.

Accesses to this register use the following encodings:

When FEAT_AMU_EXT64 is implemented

[63:0] Accessible at offset 0x100 + (8 * n) from AMU

When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011', accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0', accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

When FEAT_AMU_EXT32 is implemented

[63:0] Accessible at offset 0x100 + (8 * n) from AMU

When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011', accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0', accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACNT
ACNT