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CTIGATE

CTIGATE, CTI Channel Gate Enable register

The CTIGATE characteristics are:

Purpose

Determines whether events on channels propagate through the CTM to other ECT components, or from the CTM into the CTI.

Configuration

CTIGATE is in the Debug power domain.

Attributes

CTIGATE is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GATE31	GATE30	GATE29	GATE28	GATE27	GATE26	GATE25	GATE24	GATE23	GATE22	GATE21	GATE20	GATE19	GATE18	GATE17	GATE16	GATE15	GATE14	GATE13	GATE12	GATE11	GATE10	GATE9	GATE8	GATE7	GATE6	GATE5	GATE4	GATE3	GATE2	GATE1	GATE0

GATE<x>, bit [x], for x = 31 to 0

Channel <x> gate enable.

GATE<x>	Meaning
0b0	Disable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.
0b1	Enable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.

If GATE<x> is set to 0, no new events will be propagated to the ECT, and if the ECT supports multicycle channel events any existing output channel events will be terminated.

The reset behavior of this field is:

On an External debug reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When x >= UInt(CTIDEVID.NUMCHAN), access to this field is RAZ/WI.
Otherwise, access to this field is RW.

Accessing CTIGATE

CTIGATE can be accessed through the external debug interface:

Component	Offset	Instance
CTI	0x140	CTIGATE

Accessible as follows:

When SoftwareLockStatus(addrdesc), accesses to this register are RO.
Otherwise, accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel