ERRDEVID

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ERRDEVID, Device Configuration Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:22]

PFG, bit [21]
When RAS System Architecture v2 is implemented:

Common Fault Injection Mechanism. Describes whether any Common Fault Injection Mechanism registers are implemented in the same page as this register.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PFG	Meaning
0b0	Any Common Fault Injection Mechanism registers are implemented in the same page as this register.
0b1	Any Common Fault Injection Mechanism registers are implemented in a separate fault injection group page.

Note

The value of this field does not indicate that any Common Fault Injection Mechanism registers are implemented by the nodes in this error record group. Software must use ERR<n>FR to discover whether each node implements Common Fault Injection Mechanism registers.

Accessing this field has the following behavior:

When ERRDEVID is part of a fault injection group, access to this field is RAZ/WI.
Otherwise, access to this field is RO.

Otherwise:

Bit [20]

IRQCR, bits [19:16]

Interrupt configuration registers. Describes whether the interrupt configuration registers are implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

IRQCR	Meaning
0b0000	It is IMPLEMENTATION DEFINED whether any interrupt configuration registers are implemented.
0b0001	An IMPLEMENTATION DEFINED form of interrupt configuration registers are implemented.
0b0010	The recommended layout form of interrupt configuration registers are implemented, for simple interrupts.
0b0011	The recommended layout form of interrupt configuration registers are implemented, for message-signaled interrupts.
0b1111	Interrupt configuration registers are not implemented.

All other values are reserved.

Accessing this field has the following behavior:

When ERRDEVID is part of a fault injection group, access to this field is RAZ/WI.
Otherwise, access to this field is RO.

NUM, bits [15:0]

Highest numbered index of the error records in this group, plus one. Each implemented record is owned by a node. A node might own multiple records.

This manual describes a group of error records accessed via a standard 4KB memory-mapped peripheral. For a 4KB peripheral, up to 24 error records can be accessed if the Common Fault Injection Model is implemented, and up to 56 otherwise.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing ERRDEVID

This section shows the offset of ERRDEVID when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRDEVID.

ERRDEVID can be accessed through the memory-mapped interfaces:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0										PFG	RES0	IRQCR				NUM