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ERRGSR<m>

ERRGSR<m>, Error Group <m> Status Register, n = 0 - 13

The ERRGSR<m> characteristics are:

Purpose

Shows the status for the records in the group.

Configuration

This register is present only when FEAT_RASSAv1 is implemented. Otherwise, direct accesses to ERRGSR<m> are RES0.

ERRGSR is implemented only as part of a memory-mapped group of error records.

If FEAT_RASSA_4KB_GRP is implemented, then a single ERRGSR register is implemented.

Attributes

ERRGSR<m> is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
S63S62S61S60S59S58S57S56S55S54S53S52S51S50S49S48S47S46S45S44S43S42S41S40S39S38S37S36S35S34S33S32
S31S30S29S28S27S26S25S24S23S22S21S20S19S18S17S16S15S14S13S12S11S10S9S8S7S6S5S4S3S2S1S0

S<n>, bit [n], for n = 63 to 0

If FEAT_RASSA_4KB_GRP is implemented, the status for error record <n>. A read-only copy of ERR<n>STATUS.V.

If FEAT_RASSA_16KB_GRP is implemented or FEAT_RASSA_64KB_GRP is implemented, the status for error record <m×64+n>. A read-only copy of ERR<m×64+n>STATUS.V.

S<n>Meaning
0b0

No error.

0b1

One or more errors.

Accessing this field has the following behavior:

Accessing ERRGSR<m>

This section shows the offset of ERRGSR when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRGSR<n>.

ERRGSR<m> can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xE00 + (64 * m)ERRGSR<m>

Accesses to this register are RO.


2026-03-26 20:27:25, 2026-03_rel

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