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GICC_NSAPR<n>, CPU Interface Non-secure Active Priorities Registers, n = 0 - 3

The GICC_NSAPR<n> characteristics are:

Purpose

Provides information about Group 1 interrupt active priorities.

Configuration

This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_NSAPR<n> are RES0.

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses.

GICC_NSAPR1 is implemented only in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are implemented only in implementations that support 7 bits of priority.

Attributes

GICC_NSAPR<n> is a 32-bit register.

Field descriptions

IMPLEMENTATION DEFINED, bits [31:0]

Accessing GICC_NSAPR<n>

GICC_NSAPR<n> can be accessed through the memory-mapped interfaces:

Accessible as follows:

• When GICD_CTLR.DS == '0', accesses to this register are RW.
• When an access is Secure, accesses to this register are RW.
• When an access is Non-secure, accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel

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