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MPAMCFG_CASSOC

MPAMCFG_CASSOC, MPAM Cache Maximum Associativity Partition Configuration Register

The MPAMCFG_CASSOC characteristics are:

Purpose

The MPAMCFG_CASSOC is a 32-bit read/write register that controls the maximum fraction of the cache associativity that the PARTID selected by MPAMCFG_PART_SEL is permitted to allocate.

Configuration

The power domain of MPAMCFG_CASSOC is IMPLEMENTATION DEFINED.

This register is present only when MPAMF_IDR.HAS_CCAP_PART == '1', (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented), and MPAMF_CCAP_IDR.HAS_CASSOC == '1'. Otherwise, direct accesses to MPAMCFG_CASSOC are RES0.

If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

If FEAT_MPAMv0p1 or FEAT_MPAMv1p1 is implemented, the register is banked and the following statements apply:

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMCFG_CASSOC is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0CASSOC

Bits [31:16]

Reserved, RES0.

CASSOC, bits [15:0]

Maximum cache associativity usage in fixed-point fraction format by the partition selected by MPAMCFG_PART_SEL. The fraction represents the portion of the cache associativity that the PARTID is permitted to allocate. CASSOC controls the fraction of associativity in each associativity grouping of the cache. In a set associative cache, CASSOC applies to the fraction of the ways in each set.

The implemented width of the fixed-point fraction is given in MPAMF_CCAP_IDR.CASSOC_WD. Unimplemented bits within the field are RAZ/WI. The implemented bits of the CASSOC field are always the most significant bits of the field.

The fixed-point fraction CASSOC is less than 1. The implied binary point is between bits 15 and 16. In an implementation with w implemented bits, the largest fraction of the cache that can be represented is 1- (0.5)w.

Accessing MPAMCFG_CASSOC

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

When RIS is implemented, loads and stores to MPAMCFG_CASSOC access the cache maximum associativity partitioning configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When RIS is not implemented, loads and stores to MPAMCFG_CASSOC access the cache maximum associativity partitioning configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When PARTID narrowing is implemented, loads and stores to MPAMCFG_CASSOC access the cache maximum associativity partitioning configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.

When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CASSOC access the cache maximum associativity partitioning configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.

MPAMCFG_CASSOC can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x0118MPAMCFG_CASSOC_s

When FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x0118MPAMCFG_CASSOC_ns

When FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rt0x0118MPAMCFG_CASSOC_rt

When FEAT_RME is implemented and (FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rl0x0118MPAMCFG_CASSOC_rl

When FEAT_RME is implemented and (FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.


2026-03-26 20:27:25, 2026-03_rel

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